xref: /openbmc/qemu/hw/intc/bcm2835_ic.c (revision 28ae3179fc52d2e4d870b635c4a412aab99759e7)
1e3ece3e3SAndrew Baumann /*
2e3ece3e3SAndrew Baumann  * Raspberry Pi emulation (c) 2012 Gregory Estrade
3e3ece3e3SAndrew Baumann  * Refactoring for Pi2 Copyright (c) 2015, Microsoft. Written by Andrew Baumann.
4e3ece3e3SAndrew Baumann  * Heavily based on pl190.c, copyright terms below:
5e3ece3e3SAndrew Baumann  *
6e3ece3e3SAndrew Baumann  * Arm PrimeCell PL190 Vector Interrupt Controller
7e3ece3e3SAndrew Baumann  *
8e3ece3e3SAndrew Baumann  * Copyright (c) 2006 CodeSourcery.
9e3ece3e3SAndrew Baumann  * Written by Paul Brook
10e3ece3e3SAndrew Baumann  *
116111a0c0SPhilippe Mathieu-Daudé  * This work is licensed under the terms of the GNU GPL, version 2 or later.
126111a0c0SPhilippe Mathieu-Daudé  * See the COPYING file in the top-level directory.
13e3ece3e3SAndrew Baumann  */
14e3ece3e3SAndrew Baumann 
15c964b660SPeter Maydell #include "qemu/osdep.h"
16e3ece3e3SAndrew Baumann #include "hw/intc/bcm2835_ic.h"
1764552b6bSMarkus Armbruster #include "hw/irq.h"
18d6454270SMarkus Armbruster #include "migration/vmstate.h"
1903dd024fSPaolo Bonzini #include "qemu/log.h"
200b8fa32fSMarkus Armbruster #include "qemu/module.h"
21b68a92f4SPhilippe Mathieu-Daudé #include "trace.h"
22e3ece3e3SAndrew Baumann 
23e3ece3e3SAndrew Baumann #define GPU_IRQS 64
24e3ece3e3SAndrew Baumann #define ARM_IRQS 8
25e3ece3e3SAndrew Baumann 
26e3ece3e3SAndrew Baumann #define IRQ_PENDING_BASIC       0x00 /* IRQ basic pending */
27e3ece3e3SAndrew Baumann #define IRQ_PENDING_1           0x04 /* IRQ pending 1 */
28e3ece3e3SAndrew Baumann #define IRQ_PENDING_2           0x08 /* IRQ pending 2 */
29e3ece3e3SAndrew Baumann #define FIQ_CONTROL             0x0C /* FIQ register */
30e3ece3e3SAndrew Baumann #define IRQ_ENABLE_1            0x10 /* Interrupt enable register 1 */
31e3ece3e3SAndrew Baumann #define IRQ_ENABLE_2            0x14 /* Interrupt enable register 2 */
32e3ece3e3SAndrew Baumann #define IRQ_ENABLE_BASIC        0x18 /* Base interrupt enable register */
33e3ece3e3SAndrew Baumann #define IRQ_DISABLE_1           0x1C /* Interrupt disable register 1 */
34e3ece3e3SAndrew Baumann #define IRQ_DISABLE_2           0x20 /* Interrupt disable register 2 */
35e3ece3e3SAndrew Baumann #define IRQ_DISABLE_BASIC       0x24 /* Base interrupt disable register */
36e3ece3e3SAndrew Baumann 
37e3ece3e3SAndrew Baumann /* Update interrupts.  */
bcm2835_ic_update(BCM2835ICState * s)38e3ece3e3SAndrew Baumann static void bcm2835_ic_update(BCM2835ICState *s)
39e3ece3e3SAndrew Baumann {
40e3ece3e3SAndrew Baumann     bool set = false;
41e3ece3e3SAndrew Baumann 
42e3ece3e3SAndrew Baumann     if (s->fiq_enable) {
43e3ece3e3SAndrew Baumann         if (s->fiq_select >= GPU_IRQS) {
44e3ece3e3SAndrew Baumann             /* ARM IRQ */
45e3ece3e3SAndrew Baumann             set = extract32(s->arm_irq_level, s->fiq_select - GPU_IRQS, 1);
46e3ece3e3SAndrew Baumann         } else {
47e3ece3e3SAndrew Baumann             set = extract64(s->gpu_irq_level, s->fiq_select, 1);
48e3ece3e3SAndrew Baumann         }
49e3ece3e3SAndrew Baumann     }
50e3ece3e3SAndrew Baumann     qemu_set_irq(s->fiq, set);
51e3ece3e3SAndrew Baumann 
52e3ece3e3SAndrew Baumann     set = (s->gpu_irq_level & s->gpu_irq_enable)
53e3ece3e3SAndrew Baumann         || (s->arm_irq_level & s->arm_irq_enable);
54e3ece3e3SAndrew Baumann     qemu_set_irq(s->irq, set);
55e3ece3e3SAndrew Baumann }
56e3ece3e3SAndrew Baumann 
bcm2835_ic_set_gpu_irq(void * opaque,int irq,int level)57e3ece3e3SAndrew Baumann static void bcm2835_ic_set_gpu_irq(void *opaque, int irq, int level)
58e3ece3e3SAndrew Baumann {
59e3ece3e3SAndrew Baumann     BCM2835ICState *s = opaque;
60e3ece3e3SAndrew Baumann 
61e3ece3e3SAndrew Baumann     assert(irq >= 0 && irq < 64);
62b68a92f4SPhilippe Mathieu-Daudé     trace_bcm2835_ic_set_gpu_irq(irq, level);
63e3ece3e3SAndrew Baumann     s->gpu_irq_level = deposit64(s->gpu_irq_level, irq, 1, level != 0);
64e3ece3e3SAndrew Baumann     bcm2835_ic_update(s);
65e3ece3e3SAndrew Baumann }
66e3ece3e3SAndrew Baumann 
bcm2835_ic_set_arm_irq(void * opaque,int irq,int level)67e3ece3e3SAndrew Baumann static void bcm2835_ic_set_arm_irq(void *opaque, int irq, int level)
68e3ece3e3SAndrew Baumann {
69e3ece3e3SAndrew Baumann     BCM2835ICState *s = opaque;
70e3ece3e3SAndrew Baumann 
71e3ece3e3SAndrew Baumann     assert(irq >= 0 && irq < 8);
72b68a92f4SPhilippe Mathieu-Daudé     trace_bcm2835_ic_set_cpu_irq(irq, level);
73e3ece3e3SAndrew Baumann     s->arm_irq_level = deposit32(s->arm_irq_level, irq, 1, level != 0);
74e3ece3e3SAndrew Baumann     bcm2835_ic_update(s);
75e3ece3e3SAndrew Baumann }
76e3ece3e3SAndrew Baumann 
77e3ece3e3SAndrew Baumann static const int irq_dups[] = { 7, 9, 10, 18, 19, 53, 54, 55, 56, 57, 62 };
78e3ece3e3SAndrew Baumann 
bcm2835_ic_read(void * opaque,hwaddr offset,unsigned size)79e3ece3e3SAndrew Baumann static uint64_t bcm2835_ic_read(void *opaque, hwaddr offset, unsigned size)
80e3ece3e3SAndrew Baumann {
81e3ece3e3SAndrew Baumann     BCM2835ICState *s = opaque;
82e3ece3e3SAndrew Baumann     uint32_t res = 0;
83e3ece3e3SAndrew Baumann     uint64_t gpu_pending = s->gpu_irq_level & s->gpu_irq_enable;
84e3ece3e3SAndrew Baumann     int i;
85e3ece3e3SAndrew Baumann 
86e3ece3e3SAndrew Baumann     switch (offset) {
87e3ece3e3SAndrew Baumann     case IRQ_PENDING_BASIC:
88e3ece3e3SAndrew Baumann         /* bits 0-7: ARM irqs */
89e3ece3e3SAndrew Baumann         res = s->arm_irq_level & s->arm_irq_enable;
90e3ece3e3SAndrew Baumann 
91e3ece3e3SAndrew Baumann         /* bits 8 & 9: pending registers 1 & 2 */
92e3ece3e3SAndrew Baumann         res |= (((uint32_t)gpu_pending) != 0) << 8;
93e3ece3e3SAndrew Baumann         res |= ((gpu_pending >> 32) != 0) << 9;
94e3ece3e3SAndrew Baumann 
95e3ece3e3SAndrew Baumann         /* bits 10-20: selected GPU IRQs */
96e3ece3e3SAndrew Baumann         for (i = 0; i < ARRAY_SIZE(irq_dups); i++) {
97e3ece3e3SAndrew Baumann             res |= extract64(gpu_pending, irq_dups[i], 1) << (i + 10);
98e3ece3e3SAndrew Baumann         }
99e3ece3e3SAndrew Baumann         break;
100e3ece3e3SAndrew Baumann     case IRQ_PENDING_1:
101e3ece3e3SAndrew Baumann         res = gpu_pending;
102e3ece3e3SAndrew Baumann         break;
103e3ece3e3SAndrew Baumann     case IRQ_PENDING_2:
104e3ece3e3SAndrew Baumann         res = gpu_pending >> 32;
105e3ece3e3SAndrew Baumann         break;
106e3ece3e3SAndrew Baumann     case FIQ_CONTROL:
107e3ece3e3SAndrew Baumann         res = (s->fiq_enable << 7) | s->fiq_select;
108e3ece3e3SAndrew Baumann         break;
109e3ece3e3SAndrew Baumann     case IRQ_ENABLE_1:
110e3ece3e3SAndrew Baumann         res = s->gpu_irq_enable;
111e3ece3e3SAndrew Baumann         break;
112e3ece3e3SAndrew Baumann     case IRQ_ENABLE_2:
113e3ece3e3SAndrew Baumann         res = s->gpu_irq_enable >> 32;
114e3ece3e3SAndrew Baumann         break;
115e3ece3e3SAndrew Baumann     case IRQ_ENABLE_BASIC:
116e3ece3e3SAndrew Baumann         res = s->arm_irq_enable;
117e3ece3e3SAndrew Baumann         break;
118e3ece3e3SAndrew Baumann     case IRQ_DISABLE_1:
119e3ece3e3SAndrew Baumann         res = ~s->gpu_irq_enable;
120e3ece3e3SAndrew Baumann         break;
121e3ece3e3SAndrew Baumann     case IRQ_DISABLE_2:
122e3ece3e3SAndrew Baumann         res = ~s->gpu_irq_enable >> 32;
123e3ece3e3SAndrew Baumann         break;
124e3ece3e3SAndrew Baumann     case IRQ_DISABLE_BASIC:
125e3ece3e3SAndrew Baumann         res = ~s->arm_irq_enable;
126e3ece3e3SAndrew Baumann         break;
127e3ece3e3SAndrew Baumann     default:
128e3ece3e3SAndrew Baumann         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
129e3ece3e3SAndrew Baumann                       __func__, offset);
130e3ece3e3SAndrew Baumann         return 0;
131e3ece3e3SAndrew Baumann     }
132e3ece3e3SAndrew Baumann 
133e3ece3e3SAndrew Baumann     return res;
134e3ece3e3SAndrew Baumann }
135e3ece3e3SAndrew Baumann 
bcm2835_ic_write(void * opaque,hwaddr offset,uint64_t val,unsigned size)136e3ece3e3SAndrew Baumann static void bcm2835_ic_write(void *opaque, hwaddr offset, uint64_t val,
137e3ece3e3SAndrew Baumann                              unsigned size)
138e3ece3e3SAndrew Baumann {
139e3ece3e3SAndrew Baumann     BCM2835ICState *s = opaque;
140e3ece3e3SAndrew Baumann 
141e3ece3e3SAndrew Baumann     switch (offset) {
142e3ece3e3SAndrew Baumann     case FIQ_CONTROL:
143e3ece3e3SAndrew Baumann         s->fiq_select = extract32(val, 0, 7);
144e3ece3e3SAndrew Baumann         s->fiq_enable = extract32(val, 7, 1);
145e3ece3e3SAndrew Baumann         break;
146e3ece3e3SAndrew Baumann     case IRQ_ENABLE_1:
147e3ece3e3SAndrew Baumann         s->gpu_irq_enable |= val;
148e3ece3e3SAndrew Baumann         break;
149e3ece3e3SAndrew Baumann     case IRQ_ENABLE_2:
150e3ece3e3SAndrew Baumann         s->gpu_irq_enable |= val << 32;
151e3ece3e3SAndrew Baumann         break;
152e3ece3e3SAndrew Baumann     case IRQ_ENABLE_BASIC:
153e3ece3e3SAndrew Baumann         s->arm_irq_enable |= val & 0xff;
154e3ece3e3SAndrew Baumann         break;
155e3ece3e3SAndrew Baumann     case IRQ_DISABLE_1:
156e3ece3e3SAndrew Baumann         s->gpu_irq_enable &= ~val;
157e3ece3e3SAndrew Baumann         break;
158e3ece3e3SAndrew Baumann     case IRQ_DISABLE_2:
159e3ece3e3SAndrew Baumann         s->gpu_irq_enable &= ~(val << 32);
160e3ece3e3SAndrew Baumann         break;
161e3ece3e3SAndrew Baumann     case IRQ_DISABLE_BASIC:
162e3ece3e3SAndrew Baumann         s->arm_irq_enable &= ~val & 0xff;
163e3ece3e3SAndrew Baumann         break;
164e3ece3e3SAndrew Baumann     default:
165e3ece3e3SAndrew Baumann         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
166e3ece3e3SAndrew Baumann                       __func__, offset);
167e3ece3e3SAndrew Baumann         return;
168e3ece3e3SAndrew Baumann     }
169e3ece3e3SAndrew Baumann     bcm2835_ic_update(s);
170e3ece3e3SAndrew Baumann }
171e3ece3e3SAndrew Baumann 
172e3ece3e3SAndrew Baumann static const MemoryRegionOps bcm2835_ic_ops = {
173e3ece3e3SAndrew Baumann     .read = bcm2835_ic_read,
174e3ece3e3SAndrew Baumann     .write = bcm2835_ic_write,
175e3ece3e3SAndrew Baumann     .endianness = DEVICE_NATIVE_ENDIAN,
176e3ece3e3SAndrew Baumann     .valid.min_access_size = 4,
177e3ece3e3SAndrew Baumann     .valid.max_access_size = 4,
178e3ece3e3SAndrew Baumann };
179e3ece3e3SAndrew Baumann 
bcm2835_ic_reset(DeviceState * d)180e3ece3e3SAndrew Baumann static void bcm2835_ic_reset(DeviceState *d)
181e3ece3e3SAndrew Baumann {
182e3ece3e3SAndrew Baumann     BCM2835ICState *s = BCM2835_IC(d);
183e3ece3e3SAndrew Baumann 
184e3ece3e3SAndrew Baumann     s->gpu_irq_enable = 0;
185e3ece3e3SAndrew Baumann     s->arm_irq_enable = 0;
186e3ece3e3SAndrew Baumann     s->fiq_enable = false;
187e3ece3e3SAndrew Baumann     s->fiq_select = 0;
188e3ece3e3SAndrew Baumann }
189e3ece3e3SAndrew Baumann 
bcm2835_ic_init(Object * obj)190e3ece3e3SAndrew Baumann static void bcm2835_ic_init(Object *obj)
191e3ece3e3SAndrew Baumann {
192e3ece3e3SAndrew Baumann     BCM2835ICState *s = BCM2835_IC(obj);
193e3ece3e3SAndrew Baumann 
194e3ece3e3SAndrew Baumann     memory_region_init_io(&s->iomem, obj, &bcm2835_ic_ops, s, TYPE_BCM2835_IC,
195e3ece3e3SAndrew Baumann                           0x200);
196e3ece3e3SAndrew Baumann     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
197e3ece3e3SAndrew Baumann 
198e3ece3e3SAndrew Baumann     qdev_init_gpio_in_named(DEVICE(s), bcm2835_ic_set_gpu_irq,
199e3ece3e3SAndrew Baumann                             BCM2835_IC_GPU_IRQ, GPU_IRQS);
200e3ece3e3SAndrew Baumann     qdev_init_gpio_in_named(DEVICE(s), bcm2835_ic_set_arm_irq,
201e3ece3e3SAndrew Baumann                             BCM2835_IC_ARM_IRQ, ARM_IRQS);
202e3ece3e3SAndrew Baumann 
203e3ece3e3SAndrew Baumann     sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
204e3ece3e3SAndrew Baumann     sysbus_init_irq(SYS_BUS_DEVICE(s), &s->fiq);
205e3ece3e3SAndrew Baumann }
206e3ece3e3SAndrew Baumann 
207e3ece3e3SAndrew Baumann static const VMStateDescription vmstate_bcm2835_ic = {
208e3ece3e3SAndrew Baumann     .name = TYPE_BCM2835_IC,
209e3ece3e3SAndrew Baumann     .version_id = 1,
210e3ece3e3SAndrew Baumann     .minimum_version_id = 1,
21145b1f81dSRichard Henderson     .fields = (const VMStateField[]) {
212e3ece3e3SAndrew Baumann         VMSTATE_UINT64(gpu_irq_level, BCM2835ICState),
213e3ece3e3SAndrew Baumann         VMSTATE_UINT64(gpu_irq_enable, BCM2835ICState),
214e3ece3e3SAndrew Baumann         VMSTATE_UINT8(arm_irq_level, BCM2835ICState),
215e3ece3e3SAndrew Baumann         VMSTATE_UINT8(arm_irq_enable, BCM2835ICState),
216e3ece3e3SAndrew Baumann         VMSTATE_BOOL(fiq_enable, BCM2835ICState),
217e3ece3e3SAndrew Baumann         VMSTATE_UINT8(fiq_select, BCM2835ICState),
218e3ece3e3SAndrew Baumann         VMSTATE_END_OF_LIST()
219e3ece3e3SAndrew Baumann     }
220e3ece3e3SAndrew Baumann };
221e3ece3e3SAndrew Baumann 
bcm2835_ic_class_init(ObjectClass * klass,void * data)222e3ece3e3SAndrew Baumann static void bcm2835_ic_class_init(ObjectClass *klass, void *data)
223e3ece3e3SAndrew Baumann {
224e3ece3e3SAndrew Baumann     DeviceClass *dc = DEVICE_CLASS(klass);
225e3ece3e3SAndrew Baumann 
226*e3d08143SPeter Maydell     device_class_set_legacy_reset(dc, bcm2835_ic_reset);
227e3ece3e3SAndrew Baumann     dc->vmsd = &vmstate_bcm2835_ic;
228e3ece3e3SAndrew Baumann }
229e3ece3e3SAndrew Baumann 
2305e78c98bSBernhard Beschow static const TypeInfo bcm2835_ic_info = {
231e3ece3e3SAndrew Baumann     .name          = TYPE_BCM2835_IC,
232e3ece3e3SAndrew Baumann     .parent        = TYPE_SYS_BUS_DEVICE,
233e3ece3e3SAndrew Baumann     .instance_size = sizeof(BCM2835ICState),
234e3ece3e3SAndrew Baumann     .class_init    = bcm2835_ic_class_init,
235e3ece3e3SAndrew Baumann     .instance_init = bcm2835_ic_init,
236e3ece3e3SAndrew Baumann };
237e3ece3e3SAndrew Baumann 
bcm2835_ic_register_types(void)238e3ece3e3SAndrew Baumann static void bcm2835_ic_register_types(void)
239e3ece3e3SAndrew Baumann {
240e3ece3e3SAndrew Baumann     type_register_static(&bcm2835_ic_info);
241e3ece3e3SAndrew Baumann }
242e3ece3e3SAndrew Baumann 
243e3ece3e3SAndrew Baumann type_init(bcm2835_ic_register_types)
244