1d4451c15SAndra Danciu // SPDX-License-Identifier: GPL-2.0+
2d4451c15SAndra Danciu // imx-pcm-fiq.c -- ALSA Soc Audio Layer
3d4451c15SAndra Danciu //
4d4451c15SAndra Danciu // Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
5d4451c15SAndra Danciu //
6d4451c15SAndra Danciu // This code is based on code copyrighted by Freescale,
7d4451c15SAndra Danciu // Liam Girdwood, Javier Martin and probably others.
8d4451c15SAndra Danciu
9a23dc694SShawn Guo #include <linux/clk.h>
10a23dc694SShawn Guo #include <linux/delay.h>
11a23dc694SShawn Guo #include <linux/device.h>
12a23dc694SShawn Guo #include <linux/dma-mapping.h>
13a23dc694SShawn Guo #include <linux/init.h>
14a23dc694SShawn Guo #include <linux/interrupt.h>
15a23dc694SShawn Guo #include <linux/module.h>
16a23dc694SShawn Guo #include <linux/platform_device.h>
17a23dc694SShawn Guo #include <linux/slab.h>
18a23dc694SShawn Guo
19a23dc694SShawn Guo #include <sound/core.h>
209051cba1SMarkus Pargmann #include <sound/dmaengine_pcm.h>
21a23dc694SShawn Guo #include <sound/initval.h>
22a23dc694SShawn Guo #include <sound/pcm.h>
23a23dc694SShawn Guo #include <sound/pcm_params.h>
24a23dc694SShawn Guo #include <sound/soc.h>
25a23dc694SShawn Guo
26a23dc694SShawn Guo #include <asm/fiq.h>
27a23dc694SShawn Guo
2882906b13SArnd Bergmann #include <linux/platform_data/asoc-imx-ssi.h>
29a23dc694SShawn Guo
30a23dc694SShawn Guo #include "imx-ssi.h"
319051cba1SMarkus Pargmann #include "imx-pcm.h"
32a23dc694SShawn Guo
33a23dc694SShawn Guo struct imx_pcm_runtime_data {
342fb14880SFabio Estevam unsigned int period;
35a23dc694SShawn Guo int periods;
36a23dc694SShawn Guo unsigned long offset;
37a23dc694SShawn Guo struct hrtimer hrt;
38a23dc694SShawn Guo int poll_time_ns;
39a23dc694SShawn Guo struct snd_pcm_substream *substream;
40fc7dc61dSOskar Schirmer atomic_t playing;
41fc7dc61dSOskar Schirmer atomic_t capturing;
42a23dc694SShawn Guo };
43a23dc694SShawn Guo
snd_hrtimer_callback(struct hrtimer * hrt)44a23dc694SShawn Guo static enum hrtimer_restart snd_hrtimer_callback(struct hrtimer *hrt)
45a23dc694SShawn Guo {
46a23dc694SShawn Guo struct imx_pcm_runtime_data *iprtd =
47a23dc694SShawn Guo container_of(hrt, struct imx_pcm_runtime_data, hrt);
48a23dc694SShawn Guo struct snd_pcm_substream *substream = iprtd->substream;
49a23dc694SShawn Guo struct pt_regs regs;
50a23dc694SShawn Guo
51fc7dc61dSOskar Schirmer if (!atomic_read(&iprtd->playing) && !atomic_read(&iprtd->capturing))
52a23dc694SShawn Guo return HRTIMER_NORESTART;
53a23dc694SShawn Guo
54a23dc694SShawn Guo get_fiq_regs(®s);
55a23dc694SShawn Guo
56a23dc694SShawn Guo if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
57a23dc694SShawn Guo iprtd->offset = regs.ARM_r8 & 0xffff;
58a23dc694SShawn Guo else
59a23dc694SShawn Guo iprtd->offset = regs.ARM_r9 & 0xffff;
60a23dc694SShawn Guo
61a23dc694SShawn Guo snd_pcm_period_elapsed(substream);
62a23dc694SShawn Guo
63a23dc694SShawn Guo hrtimer_forward_now(hrt, ns_to_ktime(iprtd->poll_time_ns));
64a23dc694SShawn Guo
65a23dc694SShawn Guo return HRTIMER_RESTART;
66a23dc694SShawn Guo }
67a23dc694SShawn Guo
68a23dc694SShawn Guo static struct fiq_handler fh = {
69a23dc694SShawn Guo .name = DRV_NAME,
70a23dc694SShawn Guo };
71a23dc694SShawn Guo
snd_imx_pcm_hw_params(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)722adc3fccSKuninori Morimoto static int snd_imx_pcm_hw_params(struct snd_soc_component *component,
732adc3fccSKuninori Morimoto struct snd_pcm_substream *substream,
74a23dc694SShawn Guo struct snd_pcm_hw_params *params)
75a23dc694SShawn Guo {
76a23dc694SShawn Guo struct snd_pcm_runtime *runtime = substream->runtime;
77a23dc694SShawn Guo struct imx_pcm_runtime_data *iprtd = runtime->private_data;
78a23dc694SShawn Guo
79a23dc694SShawn Guo iprtd->periods = params_periods(params);
80a23dc694SShawn Guo iprtd->period = params_period_bytes(params);
81a23dc694SShawn Guo iprtd->offset = 0;
82a23dc694SShawn Guo iprtd->poll_time_ns = 1000000000 / params_rate(params) *
83a23dc694SShawn Guo params_period_size(params);
84a23dc694SShawn Guo
85a23dc694SShawn Guo return 0;
86a23dc694SShawn Guo }
87a23dc694SShawn Guo
snd_imx_pcm_prepare(struct snd_soc_component * component,struct snd_pcm_substream * substream)882adc3fccSKuninori Morimoto static int snd_imx_pcm_prepare(struct snd_soc_component *component,
892adc3fccSKuninori Morimoto struct snd_pcm_substream *substream)
90a23dc694SShawn Guo {
91a23dc694SShawn Guo struct snd_pcm_runtime *runtime = substream->runtime;
92a23dc694SShawn Guo struct imx_pcm_runtime_data *iprtd = runtime->private_data;
93a23dc694SShawn Guo struct pt_regs regs;
94a23dc694SShawn Guo
95a23dc694SShawn Guo get_fiq_regs(®s);
96a23dc694SShawn Guo if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
97a23dc694SShawn Guo regs.ARM_r8 = (iprtd->period * iprtd->periods - 1) << 16;
98a23dc694SShawn Guo else
99a23dc694SShawn Guo regs.ARM_r9 = (iprtd->period * iprtd->periods - 1) << 16;
100a23dc694SShawn Guo
101a23dc694SShawn Guo set_fiq_regs(®s);
102a23dc694SShawn Guo
103a23dc694SShawn Guo return 0;
104a23dc694SShawn Guo }
105a23dc694SShawn Guo
106a23dc694SShawn Guo static int imx_pcm_fiq;
107a23dc694SShawn Guo
snd_imx_pcm_trigger(struct snd_soc_component * component,struct snd_pcm_substream * substream,int cmd)1082adc3fccSKuninori Morimoto static int snd_imx_pcm_trigger(struct snd_soc_component *component,
1092adc3fccSKuninori Morimoto struct snd_pcm_substream *substream, int cmd)
110a23dc694SShawn Guo {
111a23dc694SShawn Guo struct snd_pcm_runtime *runtime = substream->runtime;
112a23dc694SShawn Guo struct imx_pcm_runtime_data *iprtd = runtime->private_data;
113a23dc694SShawn Guo
114a23dc694SShawn Guo switch (cmd) {
115a23dc694SShawn Guo case SNDRV_PCM_TRIGGER_START:
116a23dc694SShawn Guo case SNDRV_PCM_TRIGGER_RESUME:
117a23dc694SShawn Guo case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
118fc7dc61dSOskar Schirmer if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
119fc7dc61dSOskar Schirmer atomic_set(&iprtd->playing, 1);
120fc7dc61dSOskar Schirmer else
121fc7dc61dSOskar Schirmer atomic_set(&iprtd->capturing, 1);
122a23dc694SShawn Guo hrtimer_start(&iprtd->hrt, ns_to_ktime(iprtd->poll_time_ns),
123a23dc694SShawn Guo HRTIMER_MODE_REL);
124a23dc694SShawn Guo enable_fiq(imx_pcm_fiq);
125a23dc694SShawn Guo break;
126a23dc694SShawn Guo
127a23dc694SShawn Guo case SNDRV_PCM_TRIGGER_STOP:
128a23dc694SShawn Guo case SNDRV_PCM_TRIGGER_SUSPEND:
129a23dc694SShawn Guo case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
130fc7dc61dSOskar Schirmer if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
131fc7dc61dSOskar Schirmer atomic_set(&iprtd->playing, 0);
132fc7dc61dSOskar Schirmer else
133fc7dc61dSOskar Schirmer atomic_set(&iprtd->capturing, 0);
134fc7dc61dSOskar Schirmer if (!atomic_read(&iprtd->playing) &&
135fc7dc61dSOskar Schirmer !atomic_read(&iprtd->capturing))
136a23dc694SShawn Guo disable_fiq(imx_pcm_fiq);
137a23dc694SShawn Guo break;
138fc7dc61dSOskar Schirmer
139a23dc694SShawn Guo default:
140a23dc694SShawn Guo return -EINVAL;
141a23dc694SShawn Guo }
142a23dc694SShawn Guo
143a23dc694SShawn Guo return 0;
144a23dc694SShawn Guo }
145a23dc694SShawn Guo
1462adc3fccSKuninori Morimoto static snd_pcm_uframes_t
snd_imx_pcm_pointer(struct snd_soc_component * component,struct snd_pcm_substream * substream)1472adc3fccSKuninori Morimoto snd_imx_pcm_pointer(struct snd_soc_component *component,
1482adc3fccSKuninori Morimoto struct snd_pcm_substream *substream)
149a23dc694SShawn Guo {
150a23dc694SShawn Guo struct snd_pcm_runtime *runtime = substream->runtime;
151a23dc694SShawn Guo struct imx_pcm_runtime_data *iprtd = runtime->private_data;
152a23dc694SShawn Guo
153a23dc694SShawn Guo return bytes_to_frames(substream->runtime, iprtd->offset);
154a23dc694SShawn Guo }
155a23dc694SShawn Guo
156f77bb3b7SBhumika Goyal static const struct snd_pcm_hardware snd_imx_hardware = {
157a23dc694SShawn Guo .info = SNDRV_PCM_INFO_INTERLEAVED |
158a23dc694SShawn Guo SNDRV_PCM_INFO_BLOCK_TRANSFER |
159a23dc694SShawn Guo SNDRV_PCM_INFO_MMAP |
160a23dc694SShawn Guo SNDRV_PCM_INFO_MMAP_VALID |
161a23dc694SShawn Guo SNDRV_PCM_INFO_PAUSE |
162a23dc694SShawn Guo SNDRV_PCM_INFO_RESUME,
163a23dc694SShawn Guo .formats = SNDRV_PCM_FMTBIT_S16_LE,
164a23dc694SShawn Guo .buffer_bytes_max = IMX_SSI_DMABUF_SIZE,
165a23dc694SShawn Guo .period_bytes_min = 128,
166a23dc694SShawn Guo .period_bytes_max = 16 * 1024,
167a23dc694SShawn Guo .periods_min = 4,
168a23dc694SShawn Guo .periods_max = 255,
169a23dc694SShawn Guo .fifo_size = 0,
170a23dc694SShawn Guo };
171a23dc694SShawn Guo
snd_imx_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)1722adc3fccSKuninori Morimoto static int snd_imx_open(struct snd_soc_component *component,
1732adc3fccSKuninori Morimoto struct snd_pcm_substream *substream)
174a23dc694SShawn Guo {
175a23dc694SShawn Guo struct snd_pcm_runtime *runtime = substream->runtime;
176a23dc694SShawn Guo struct imx_pcm_runtime_data *iprtd;
177a23dc694SShawn Guo int ret;
178a23dc694SShawn Guo
179a23dc694SShawn Guo iprtd = kzalloc(sizeof(*iprtd), GFP_KERNEL);
180a23dc694SShawn Guo if (iprtd == NULL)
181a23dc694SShawn Guo return -ENOMEM;
182a23dc694SShawn Guo runtime->private_data = iprtd;
183a23dc694SShawn Guo
184a23dc694SShawn Guo iprtd->substream = substream;
185a23dc694SShawn Guo
186fc7dc61dSOskar Schirmer atomic_set(&iprtd->playing, 0);
187fc7dc61dSOskar Schirmer atomic_set(&iprtd->capturing, 0);
188a23dc694SShawn Guo hrtimer_init(&iprtd->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
189a23dc694SShawn Guo iprtd->hrt.function = snd_hrtimer_callback;
190a23dc694SShawn Guo
191a23dc694SShawn Guo ret = snd_pcm_hw_constraint_integer(substream->runtime,
192a23dc694SShawn Guo SNDRV_PCM_HW_PARAM_PERIODS);
193a23dc694SShawn Guo if (ret < 0) {
194a23dc694SShawn Guo kfree(iprtd);
195a23dc694SShawn Guo return ret;
196a23dc694SShawn Guo }
197a23dc694SShawn Guo
198a23dc694SShawn Guo snd_soc_set_runtime_hwparams(substream, &snd_imx_hardware);
199a23dc694SShawn Guo return 0;
200a23dc694SShawn Guo }
201a23dc694SShawn Guo
snd_imx_close(struct snd_soc_component * component,struct snd_pcm_substream * substream)2022adc3fccSKuninori Morimoto static int snd_imx_close(struct snd_soc_component *component,
2032adc3fccSKuninori Morimoto struct snd_pcm_substream *substream)
204a23dc694SShawn Guo {
205a23dc694SShawn Guo struct snd_pcm_runtime *runtime = substream->runtime;
206a23dc694SShawn Guo struct imx_pcm_runtime_data *iprtd = runtime->private_data;
207a23dc694SShawn Guo
208a23dc694SShawn Guo hrtimer_cancel(&iprtd->hrt);
209a23dc694SShawn Guo
210a23dc694SShawn Guo kfree(iprtd);
211a23dc694SShawn Guo
212a23dc694SShawn Guo return 0;
213a23dc694SShawn Guo }
214a23dc694SShawn Guo
imx_pcm_new(struct snd_soc_pcm_runtime * rtd)215dbdf6b54SShawn Guo static int imx_pcm_new(struct snd_soc_pcm_runtime *rtd)
216dbdf6b54SShawn Guo {
217dbdf6b54SShawn Guo struct snd_card *card = rtd->card->snd_card;
218dbdf6b54SShawn Guo struct snd_pcm *pcm = rtd->pcm;
219c9bd5e69SRussell King int ret;
220dbdf6b54SShawn Guo
221c9bd5e69SRussell King ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
222c9bd5e69SRussell King if (ret)
223c9bd5e69SRussell King return ret;
224c9bd5e69SRussell King
225*f010a498STakashi Iwai return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_WC,
226*f010a498STakashi Iwai pcm->card->dev,
227*f010a498STakashi Iwai IMX_SSI_DMABUF_SIZE);
228dbdf6b54SShawn Guo }
229dbdf6b54SShawn Guo
230cb7d53b4SAlin Grigorean static int ssi_irq;
231a23dc694SShawn Guo
snd_imx_pcm_new(struct snd_soc_component * component,struct snd_soc_pcm_runtime * rtd)2322adc3fccSKuninori Morimoto static int snd_imx_pcm_new(struct snd_soc_component *component,
2332adc3fccSKuninori Morimoto struct snd_soc_pcm_runtime *rtd)
234a23dc694SShawn Guo {
235a23dc694SShawn Guo struct snd_pcm *pcm = rtd->pcm;
236a23dc694SShawn Guo struct snd_pcm_substream *substream;
237a23dc694SShawn Guo int ret;
238a23dc694SShawn Guo
239a23dc694SShawn Guo ret = imx_pcm_new(rtd);
240a23dc694SShawn Guo if (ret)
241a23dc694SShawn Guo return ret;
242a23dc694SShawn Guo
243a23dc694SShawn Guo substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
244a23dc694SShawn Guo if (substream) {
245a23dc694SShawn Guo struct snd_dma_buffer *buf = &substream->dma_buffer;
246a23dc694SShawn Guo
247a23dc694SShawn Guo imx_ssi_fiq_tx_buffer = (unsigned long)buf->area;
248a23dc694SShawn Guo }
249a23dc694SShawn Guo
250a23dc694SShawn Guo substream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
251a23dc694SShawn Guo if (substream) {
252a23dc694SShawn Guo struct snd_dma_buffer *buf = &substream->dma_buffer;
253a23dc694SShawn Guo
254a23dc694SShawn Guo imx_ssi_fiq_rx_buffer = (unsigned long)buf->area;
255a23dc694SShawn Guo }
256a23dc694SShawn Guo
257a23dc694SShawn Guo set_fiq_handler(&imx_ssi_fiq_start,
258a23dc694SShawn Guo &imx_ssi_fiq_end - &imx_ssi_fiq_start);
259a23dc694SShawn Guo
260a23dc694SShawn Guo return 0;
261a23dc694SShawn Guo }
262a23dc694SShawn Guo
snd_imx_pcm_free(struct snd_soc_component * component,struct snd_pcm * pcm)2632adc3fccSKuninori Morimoto static void snd_imx_pcm_free(struct snd_soc_component *component,
2642adc3fccSKuninori Morimoto struct snd_pcm *pcm)
265a23dc694SShawn Guo {
266a23dc694SShawn Guo mxc_set_irq_fiq(ssi_irq, 0);
267a23dc694SShawn Guo release_fiq(&fh);
268a23dc694SShawn Guo }
269a23dc694SShawn Guo
2701d0a01f2SKuninori Morimoto static const struct snd_soc_component_driver imx_soc_component_fiq = {
2712adc3fccSKuninori Morimoto .open = snd_imx_open,
2722adc3fccSKuninori Morimoto .close = snd_imx_close,
2732adc3fccSKuninori Morimoto .hw_params = snd_imx_pcm_hw_params,
2742adc3fccSKuninori Morimoto .prepare = snd_imx_pcm_prepare,
2752adc3fccSKuninori Morimoto .trigger = snd_imx_pcm_trigger,
2762adc3fccSKuninori Morimoto .pointer = snd_imx_pcm_pointer,
2772adc3fccSKuninori Morimoto .pcm_construct = snd_imx_pcm_new,
2782adc3fccSKuninori Morimoto .pcm_destruct = snd_imx_pcm_free,
279a23dc694SShawn Guo };
280a23dc694SShawn Guo
imx_pcm_fiq_init(struct platform_device * pdev,struct imx_pcm_fiq_params * params)2819051cba1SMarkus Pargmann int imx_pcm_fiq_init(struct platform_device *pdev,
2829051cba1SMarkus Pargmann struct imx_pcm_fiq_params *params)
283a23dc694SShawn Guo {
284a23dc694SShawn Guo int ret;
285a23dc694SShawn Guo
286a23dc694SShawn Guo ret = claim_fiq(&fh);
287a23dc694SShawn Guo if (ret) {
288a23dc694SShawn Guo dev_err(&pdev->dev, "failed to claim fiq: %d", ret);
289a23dc694SShawn Guo return ret;
290a23dc694SShawn Guo }
291a23dc694SShawn Guo
2929051cba1SMarkus Pargmann mxc_set_irq_fiq(params->irq, 1);
2939051cba1SMarkus Pargmann ssi_irq = params->irq;
294a23dc694SShawn Guo
2959051cba1SMarkus Pargmann imx_pcm_fiq = params->irq;
296a23dc694SShawn Guo
2979051cba1SMarkus Pargmann imx_ssi_fiq_base = (unsigned long)params->base;
298a23dc694SShawn Guo
2999051cba1SMarkus Pargmann params->dma_params_tx->maxburst = 4;
3009051cba1SMarkus Pargmann params->dma_params_rx->maxburst = 6;
301a23dc694SShawn Guo
3021d0a01f2SKuninori Morimoto ret = devm_snd_soc_register_component(&pdev->dev, &imx_soc_component_fiq,
3031d0a01f2SKuninori Morimoto NULL, 0);
304a23dc694SShawn Guo if (ret)
305a23dc694SShawn Guo goto failed_register;
306a23dc694SShawn Guo
307a23dc694SShawn Guo return 0;
308a23dc694SShawn Guo
309a23dc694SShawn Guo failed_register:
310a23dc694SShawn Guo mxc_set_irq_fiq(ssi_irq, 0);
311a23dc694SShawn Guo release_fiq(&fh);
312a23dc694SShawn Guo
313a23dc694SShawn Guo return ret;
314a23dc694SShawn Guo }
315dbdf6b54SShawn Guo EXPORT_SYMBOL_GPL(imx_pcm_fiq_init);
31688e89f55SShawn Guo
imx_pcm_fiq_exit(struct platform_device * pdev)31788e89f55SShawn Guo void imx_pcm_fiq_exit(struct platform_device *pdev)
31888e89f55SShawn Guo {
31988e89f55SShawn Guo }
320dbdf6b54SShawn Guo EXPORT_SYMBOL_GPL(imx_pcm_fiq_exit);
3213c1c32d3SMark Brown
3223c1c32d3SMark Brown MODULE_LICENSE("GPL");
323