Home
last modified time | relevance | path

Searched full:equalization (Results 1 – 25 of 52) sorted by relevance

123

/openbmc/linux/drivers/gpu/drm/tegra/
H A Ddp.h31 * training pattern sequence 3 supported for equalization
97 * @channel_equalized: flag to track if channel equalization has completed
131 * @ce: channel equalization read interval
H A Ddp.c209 * and channel equalization should use 100 us or 400 us AUX read in drm_dp_link_probe()
681 /* start channel equalization using pattern 2 or 3 */ in drm_dp_link_channel_equalization()
767 DRM_ERROR("channel equalization failed: %d\n", err); in drm_dp_link_train_full()
772 DRM_ERROR("channel equalization failed, downgrading link\n"); in drm_dp_link_train_full()
781 DRM_DEBUG_KMS("channel equalization succeeded\n"); in drm_dp_link_train_full()
836 DRM_ERROR("channel equalization failed\n"); in drm_dp_link_train_fast()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_dpia.c577 /* Return status read interval during equalization phase. */
599 /* Execute equalization phase of link training for specified hop in display
642 /* DPTX-to-DPIA equalization always successful. */ in dpia_training_eq_non_transparent()
734 /* Abort link training if equalization failed due to HPD unplug. */ in dpia_training_eq_non_transparent()
739 "%s\n DPIA(%d) equalization\n - hop(%d)\n - result(%d)\n - retries(%d)\n - status(%d)\n", in dpia_training_eq_non_transparent()
750 /* Execute equalization phase of link training for specified hop in display
753 * - driver writes TPSx to DPCD to notify DPIA that is in equalization phase.
754 * - equalization (EQ) for link is handled by DPOA, which reports result to DPIA on completion.
825 /* Abort link training if equalization failed due to HPD unplug. */ in dpia_training_eq_transparent()
829 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) equalization\n - hop(%d)\n - result(%d)\n - retries(%d)\n", in dpia_training_eq_transparent()
[all …]
H A Dlink_dp_training_auxless.c62 /* transmit training pattern for channel equalization. */ in dp_perform_link_training_skip_aux()
/openbmc/u-boot/drivers/video/
H A Dlogicore_dp_tx.c44 * @TS_CHANNEL_EQUALIZATION: State for channel equalization
193 * equalization, symbol lock, and interlane alignment. The remaining 2 bytes
1030 /* delay for the channel equalization phase. */ in get_training_delay()
1241 * check_channel_equalization() - Check channel equalization success
1243 * @lane_count: The number of lanes for which to check channel equalization
1247 * that the channel equalization sequence during link training was successful -
1248 * the RX device has achieved channel equalization, symbol lock, and interlane
1251 * Return: 0 if channel equalization was successful on all lanes in question,
1275 /* All (lane_count) lanes have achieved channel equalization. */ in check_channel_equalization()
1466 * training_state_channel_equalization() - Run channel equalization part of
[all …]
H A Dlogicore_dp_tx_regif.h154 /* training pattern 2 used for channel equalization */
157 * training pattern 3 used for channel equalization for cores with DP
/openbmc/u-boot/drivers/misc/
H A Dmpc83xx_serdes.h14 * @SRDSCR0_TXEQA_MASK: Bitmask for the TXEQA (transmit equalization for
17 * @SRDSCR0_TXEQE_MASK: Bitmask for the TXEQE (transmit equalization for
/openbmc/linux/drivers/infiniband/hw/hfi1/
H A Dqsfp.h66 /* Active Equalization includes fiber, copper full EQ, and copper near Eq */
68 /* Active Equalization includes fiber, copper full EQ, and copper far Eq */
H A Dpcie.c640 /* equalization columns */
645 /* discrete silicon preliminary equalization values */
661 /* integrated silicon preliminary equalization values */
1046 * Leave at reset value. No need to set PerfEq - link equalization in do_pcie_gen3_transition()
1143 /* disable pCal for PCIe Gen3 RX equalization */ in do_pcie_gen3_transition()
1148 * Enable iCal for PCIe Gen3 RX equalization, and set which in do_pcie_gen3_transition()
/openbmc/linux/drivers/infiniband/hw/qib/
H A Dqib_qsfp.h81 /* Active Equalization includes fiber, copper full EQ, and copper near Eq */
83 /* Active Equalization includes fiber, copper full EQ, and copper far Eq */
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_tv_regs.h260 /* Enables generation of the equalization signal */
265 /* Offset of the start of equalization in field 1, measured in one less than
271 * Offset of the start of equalization in field 2, measured in one less than
H A Dintel_dp_link_training.c904 * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2
961 * Perform the link training channel equalization phase on the given DP PHY
985 /* channel equalization */ in intel_dp_link_training_channel_equalization()
988 lt_err(intel_dp, dp_phy, "Failed to start channel equalization\n"); in intel_dp_link_training_channel_equalization()
1006 "Clock recovery check failed, cannot continue channel equalization\n"); in intel_dp_link_training_channel_equalization()
1029 lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n"); in intel_dp_link_training_channel_equalization()
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch3.h510 u32 rec0; /* Receive Equalization Control 0 */
511 u32 rec1; /* Receive Equalization Control 1 */
512 u32 tec0; /* Transmit Equalization Control 0 */
H A Dimmap_lsch2.h619 u32 recr0; /* 0x810 Receive Equalization Control */
621 u32 tecr0; /* 0x818 Transmit Equalization Control */
/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dimmap_ls102xa.h383 u32 recr0; /* 0x810 Receive Equalization Control */
385 u32 tecr0; /* 0x818 Transmit Equalization Control */
/openbmc/linux/drivers/net/ethernet/realtek/
H A DKconfig69 bool "Support for uncommon RTL-8139 rev. K (automatic channel equalization)"
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dbaikal,bt1-pcie.yaml42 MSI, AER, PME, Hot-plug, Link Bandwidth Management, Link Equalization
H A Dsnps,dw-pcie-ep.yaml130 Link Equalization Request flag is set in the Link Status 2
H A Dsnps,dw-pcie.yaml139 Link Equalization Request flag is set in the Link Status 2
H A Dsnps,dw-pcie-common.yaml52 bandwidth change, link equalization request, INTx asserted/deasserted
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-av-core.c302 * 5 (625) or 6 (525) half-lines of equalization pulses in cx18_av_std_setup()
308 * 10 = vblank656 - vblank = vsync pulses + equalization pulses in cx18_av_std_setup()
319 * 5 or 4 equalization pulses (start of line 6 or 318) in cx18_av_std_setup()
380 * 12 = vblank656 - vblank = vsync pulses + equalization pulses in cx18_av_std_setup()
391 * 6 or 5 equalization pulses (start of line 10 or 272) in cx18_av_std_setup()
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dcirrus,cs35l41.yaml14 speaker protection and equalization
/openbmc/linux/drivers/phy/freescale/
H A Dphy-fsl-lynx-28g.c289 /* Configure the appropriate equalization parameters for the protocol */ in lynx_28g_lane_set_sgmii()
325 /* Configure the appropriate equalization parameters for the protocol */ in lynx_28g_lane_set_10gbaser()
/openbmc/linux/drivers/phy/amlogic/
H A Dphy-meson-g12a-usb3-pcie.c227 * Fix RX Equalization setting as follows in phy_g12a_usb3_init()
/openbmc/linux/drivers/scsi/isci/
H A Dhost.c1935 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement in sci_controller_afe_initialization()
2050 /* Enable TX equalization (0xe824) */ in sci_controller_afe_initialization()
2073 /* Enable TX equalization (0xe824) */ in sci_controller_afe_initialization()
2082 /* Enable TX equalization (0xe824) */ in sci_controller_afe_initialization()
2098 /* Enable TX equalization (0xe824) */ in sci_controller_afe_initialization()

123