xref: /openbmc/linux/drivers/gpu/drm/tegra/dp.h (revision c95baf12f5077419db01313ab61c2aac007d40cd)
19a42c7c6SThierry Reding /* SPDX-License-Identifier: MIT */
29a42c7c6SThierry Reding /*
39a42c7c6SThierry Reding  * Copyright (C) 2013-2019 NVIDIA Corporation.
49a42c7c6SThierry Reding  * Copyright (C) 2015 Rob Clark
59a42c7c6SThierry Reding  */
69a42c7c6SThierry Reding 
79a42c7c6SThierry Reding #ifndef DRM_TEGRA_DP_H
89a42c7c6SThierry Reding #define DRM_TEGRA_DP_H 1
99a42c7c6SThierry Reding 
1027ba465cSThierry Reding #include <linux/types.h>
1127ba465cSThierry Reding 
1201f09f24SThierry Reding struct drm_display_info;
1301f09f24SThierry Reding struct drm_display_mode;
149a42c7c6SThierry Reding struct drm_dp_aux;
15*078c4457SThierry Reding struct drm_dp_link;
169a42c7c6SThierry Reding 
1727ba465cSThierry Reding /**
1827ba465cSThierry Reding  * struct drm_dp_link_caps - DP link capabilities
1927ba465cSThierry Reding  */
2027ba465cSThierry Reding struct drm_dp_link_caps {
2127ba465cSThierry Reding 	/**
2227ba465cSThierry Reding 	 * @enhanced_framing:
2327ba465cSThierry Reding 	 *
2427ba465cSThierry Reding 	 * enhanced framing capability (mandatory as of DP 1.2)
2527ba465cSThierry Reding 	 */
2627ba465cSThierry Reding 	bool enhanced_framing;
27cb072eebSThierry Reding 
28cb072eebSThierry Reding 	/**
29db199502SThierry Reding 	 * tps3_supported:
30db199502SThierry Reding 	 *
31db199502SThierry Reding 	 * training pattern sequence 3 supported for equalization
32db199502SThierry Reding 	 */
33db199502SThierry Reding 	bool tps3_supported;
34db199502SThierry Reding 
35db199502SThierry Reding 	/**
36cb072eebSThierry Reding 	 * @fast_training:
37cb072eebSThierry Reding 	 *
38cb072eebSThierry Reding 	 * AUX CH handshake not required for link training
39cb072eebSThierry Reding 	 */
40cb072eebSThierry Reding 	bool fast_training;
416c651b13SThierry Reding 
426c651b13SThierry Reding 	/**
436c651b13SThierry Reding 	 * @channel_coding:
446c651b13SThierry Reding 	 *
456c651b13SThierry Reding 	 * ANSI 8B/10B channel coding capability
466c651b13SThierry Reding 	 */
476c651b13SThierry Reding 	bool channel_coding;
484ff9ba56SThierry Reding 
494ff9ba56SThierry Reding 	/**
504ff9ba56SThierry Reding 	 * @alternate_scrambler_reset:
514ff9ba56SThierry Reding 	 *
524ff9ba56SThierry Reding 	 * eDP alternate scrambler reset capability
534ff9ba56SThierry Reding 	 */
544ff9ba56SThierry Reding 	bool alternate_scrambler_reset;
5527ba465cSThierry Reding };
5627ba465cSThierry Reding 
5727ba465cSThierry Reding void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
5827ba465cSThierry Reding 			   const struct drm_dp_link_caps *src);
599a42c7c6SThierry Reding 
600fa5c1bdSThierry Reding /**
61*078c4457SThierry Reding  * struct drm_dp_link_ops - DP link operations
62*078c4457SThierry Reding  */
63*078c4457SThierry Reding struct drm_dp_link_ops {
64*078c4457SThierry Reding 	/**
65*078c4457SThierry Reding 	 * @apply_training:
66*078c4457SThierry Reding 	 */
67*078c4457SThierry Reding 	int (*apply_training)(struct drm_dp_link *link);
68*078c4457SThierry Reding 
69*078c4457SThierry Reding 	/**
70*078c4457SThierry Reding 	 * @configure:
71*078c4457SThierry Reding 	 */
72*078c4457SThierry Reding 	int (*configure)(struct drm_dp_link *link);
73*078c4457SThierry Reding };
74*078c4457SThierry Reding 
75*078c4457SThierry Reding #define DP_TRAIN_VOLTAGE_SWING_LEVEL(x) ((x) << 0)
76*078c4457SThierry Reding #define DP_TRAIN_PRE_EMPHASIS_LEVEL(x) ((x) << 3)
77*078c4457SThierry Reding #define DP_LANE_POST_CURSOR(i, x) (((x) & 0x3) << (((i) & 1) << 2))
78*078c4457SThierry Reding 
79*078c4457SThierry Reding /**
80*078c4457SThierry Reding  * struct drm_dp_link_train_set - link training settings
81*078c4457SThierry Reding  * @voltage_swing: per-lane voltage swing
82*078c4457SThierry Reding  * @pre_emphasis: per-lane pre-emphasis
83*078c4457SThierry Reding  * @post_cursor: per-lane post-cursor
84*078c4457SThierry Reding  */
85*078c4457SThierry Reding struct drm_dp_link_train_set {
86*078c4457SThierry Reding 	unsigned int voltage_swing[4];
87*078c4457SThierry Reding 	unsigned int pre_emphasis[4];
88*078c4457SThierry Reding 	unsigned int post_cursor[4];
89*078c4457SThierry Reding };
90*078c4457SThierry Reding 
91*078c4457SThierry Reding /**
92*078c4457SThierry Reding  * struct drm_dp_link_train - link training state information
93*078c4457SThierry Reding  * @request: currently requested settings
94*078c4457SThierry Reding  * @adjust: adjustments requested by sink
95*078c4457SThierry Reding  * @pattern: currently requested training pattern
96*078c4457SThierry Reding  * @clock_recovered: flag to track if clock recovery has completed
97*078c4457SThierry Reding  * @channel_equalized: flag to track if channel equalization has completed
98*078c4457SThierry Reding  */
99*078c4457SThierry Reding struct drm_dp_link_train {
100*078c4457SThierry Reding 	struct drm_dp_link_train_set request;
101*078c4457SThierry Reding 	struct drm_dp_link_train_set adjust;
102*078c4457SThierry Reding 
103*078c4457SThierry Reding 	unsigned int pattern;
104*078c4457SThierry Reding 
105*078c4457SThierry Reding 	bool clock_recovered;
106*078c4457SThierry Reding 	bool channel_equalized;
107*078c4457SThierry Reding };
108*078c4457SThierry Reding 
109*078c4457SThierry Reding /**
110c728e2d4SThierry Reding  * struct drm_dp_link - DP link capabilities and configuration
1110fa5c1bdSThierry Reding  * @revision: DP specification revision supported on the link
112c728e2d4SThierry Reding  * @max_rate: maximum clock rate supported on the link
113c728e2d4SThierry Reding  * @max_lanes: maximum number of lanes supported on the link
11427ba465cSThierry Reding  * @caps: capabilities supported on the link (see &drm_dp_link_caps)
115ad7f2ddaSThierry Reding  * @aux_rd_interval: AUX read interval to use for training (in microseconds)
1167aa3cc54SThierry Reding  * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...)
117c728e2d4SThierry Reding  * @rate: currently configured link rate
118c728e2d4SThierry Reding  * @lanes: currently configured number of lanes
1196a127160SThierry Reding  * @rates: additional supported link rates in kHz (eDP 1.4)
1206a127160SThierry Reding  * @num_rates: number of additional supported link rates (eDP 1.4)
1210fa5c1bdSThierry Reding  */
1229a42c7c6SThierry Reding struct drm_dp_link {
1239a42c7c6SThierry Reding 	unsigned char revision;
124c728e2d4SThierry Reding 	unsigned int max_rate;
125c728e2d4SThierry Reding 	unsigned int max_lanes;
12627ba465cSThierry Reding 
12727ba465cSThierry Reding 	struct drm_dp_link_caps caps;
128ad7f2ddaSThierry Reding 
129ad7f2ddaSThierry Reding 	/**
130ad7f2ddaSThierry Reding 	 * @cr: clock recovery read interval
131ad7f2ddaSThierry Reding 	 * @ce: channel equalization read interval
132ad7f2ddaSThierry Reding 	 */
133ad7f2ddaSThierry Reding 	struct {
134ad7f2ddaSThierry Reding 		unsigned int cr;
135ad7f2ddaSThierry Reding 		unsigned int ce;
136ad7f2ddaSThierry Reding 	} aux_rd_interval;
137ad7f2ddaSThierry Reding 
1387aa3cc54SThierry Reding 	unsigned char edp;
139c728e2d4SThierry Reding 
140c728e2d4SThierry Reding 	unsigned int rate;
141c728e2d4SThierry Reding 	unsigned int lanes;
1426a127160SThierry Reding 
1436a127160SThierry Reding 	unsigned long rates[DP_MAX_SUPPORTED_RATES];
1446a127160SThierry Reding 	unsigned int num_rates;
145*078c4457SThierry Reding 
146*078c4457SThierry Reding 	/**
147*078c4457SThierry Reding 	 * @ops: DP link operations
148*078c4457SThierry Reding 	 */
149*078c4457SThierry Reding 	const struct drm_dp_link_ops *ops;
150*078c4457SThierry Reding 
151*078c4457SThierry Reding 	/**
152*078c4457SThierry Reding 	 * @aux: DP AUX channel
153*078c4457SThierry Reding 	 */
154*078c4457SThierry Reding 	struct drm_dp_aux *aux;
155*078c4457SThierry Reding 
156*078c4457SThierry Reding 	/**
157*078c4457SThierry Reding 	 * @train: DP link training state
158*078c4457SThierry Reding 	 */
159*078c4457SThierry Reding 	struct drm_dp_link_train train;
1609a42c7c6SThierry Reding };
1619a42c7c6SThierry Reding 
1626a127160SThierry Reding int drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate);
1636a127160SThierry Reding int drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate);
1646a127160SThierry Reding void drm_dp_link_update_rates(struct drm_dp_link *link);
1656a127160SThierry Reding 
1669a42c7c6SThierry Reding int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
1679a42c7c6SThierry Reding int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
1689a42c7c6SThierry Reding int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
1699a42c7c6SThierry Reding int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
17001f09f24SThierry Reding int drm_dp_link_choose(struct drm_dp_link *link,
17101f09f24SThierry Reding 		       const struct drm_display_mode *mode,
17201f09f24SThierry Reding 		       const struct drm_display_info *info);
1739a42c7c6SThierry Reding 
174*078c4457SThierry Reding void drm_dp_link_train_init(struct drm_dp_link_train *train);
175*078c4457SThierry Reding int drm_dp_link_train(struct drm_dp_link *link);
176*078c4457SThierry Reding 
1779a42c7c6SThierry Reding #endif
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