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/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7m/
H A Dtune-cortexm3.inc2 # Tune Settings for Cortex-M3
6 TUNEVALID[cortexm3] = "Enable Cortex-M3 specific processor optimizations"
7 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexm3', ' -mcpu=cortex-m3', '', d)}"
9 require conf/machine/include/arm/arch-armv7m.inc
12 ARMPKGARCH:tune-cortexm3 = "cortexm3"
13 TUNE_FEATURES:tune-cortexm3 = "${TUNE_FEATURES:tune-armv7m} cortexm3"
14 PACKAGE_EXTRA_ARCHS:tune-cortexm3 = "${PACKAGE_EXTRA_ARCHS:tune-armv7m} cortexm3"
/openbmc/qemu/docs/system/arm/
H A Dstm32.rst1 STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olimex-stm32-h405``, ``stm32vl…
4 The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
7 .. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
9 The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
12 - ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcontroller
14 The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
17 - ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller
19 The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L4
20 ultra-low-power series. The STM32F4 series is pin-to-pin compatible with STM32F2 series.
21 The following machines are based on this ARM Cortex-M4F chip :
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H A Dstellaris.rst7 - Cortex-M3 CPU core.
9 - 64k Flash and 8k SRAM.
11 - Timers, UARTs, ADC and |I2C| interface.
13 - OSRAM Pictiva 96x16 OLED with SSD0303 controller on
19 - Cortex-M3 CPU core.
21 - 256k Flash and 64k SRAM.
23 - Timers, UARTs, ADC, |I2C| and SSI interfaces.
25 - OSRAM Pictiva 128x64 OLED with SSD0323 controller connected via
H A Dmps2.rst1 …ards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521…
4 These board models use Arm M-profile or R-profile CPUs.
16 FPGA images using M-profile CPUs:
18 ``mps2-an385``
19 Cortex-M3 as documented in Arm Application Note AN385
20 ``mps2-an386``
21 Cortex-M4 as documented in Arm Application Note AN386
22 ``mps2-an500``
23 Cortex-M7 as documented in Arm Application Note AN500
24 ``mps2-an505``
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/openbmc/qemu/hw/arm/
H A Dmps2.c17 * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
18 * "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
19 * "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500
20 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
24 * https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
31 #include "qemu/error-report.h"
34 #include "hw/or-irq.h"
36 #include "exec/address-spaces.h"
38 #include "hw/qdev-properties.h"
40 #include "hw/char/cmsdk-apb-uart.h"
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H A Dnetduino2.c28 #include "hw/qdev-properties.h"
29 #include "hw/qdev-clock.h"
30 #include "qemu/error-report.h"
42 /* This clock doesn't need migration because it is fixed-frequency */ in netduino2_init()
51 armv7m_load_kernel(STM32F205_SOC(dev)->armv7m.cpu, machine->kernel_filename, in netduino2_init()
58 ARM_CPU_TYPE_NAME("cortex-m3"), in netduino2_machine_init()
62 mc->desc = "Netduino 2 Machine (Cortex-M3)"; in netduino2_machine_init()
63 mc->init = netduino2_init; in netduino2_machine_init()
64 mc->valid_cpu_types = valid_cpu_types; in netduino2_machine_init()
65 mc->ignore_memory_transaction_failures = true; in netduino2_machine_init()
H A Dstm32vldiscovery.c29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-clock.h"
31 #include "qemu/error-report.h"
45 /* This clock doesn't need migration because it is fixed-frequency */ in stm32vldiscovery_init()
54 armv7m_load_kernel(STM32F100_SOC(dev)->armv7m.cpu, in stm32vldiscovery_init()
55 machine->kernel_filename, in stm32vldiscovery_init()
62 ARM_CPU_TYPE_NAME("cortex-m3"), in stm32vldiscovery_machine_init()
66 mc->desc = "ST STM32VLDISCOVERY (Cortex-M3)"; in stm32vldiscovery_machine_init()
67 mc->init = stm32vldiscovery_init; in stm32vldiscovery_machine_init()
68 mc->valid_cpu_types = valid_cpu_types; in stm32vldiscovery_machine_init()
H A Dmsf2-soc.c4 * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>
28 #include "exec/address-spaces.h"
29 #include "hw/char/serial-mm.h"
30 #include "hw/arm/msf2-soc.h"
32 #include "hw/qdev-clock.h"
66 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in m2sxxx_soc_initfn()
68 object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG); in m2sxxx_soc_initfn()
70 object_initialize_child(obj, "timer", &s->timer, TYPE_MSS_TIMER); in m2sxxx_soc_initfn()
73 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI); in m2sxxx_soc_initfn()
76 object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC); in m2sxxx_soc_initfn()
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/openbmc/linux/Documentation/devicetree/bindings/soc/renesas/
H A Drenesas.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas SH-Mobile, R-Mobile, and R-Car Platform
10 - Geert Uytterhoeven <geert+renesas@glider.be>
17 - description: Emma Mobile EV2
19 - enum:
20 - renesas,kzm9d # Kyoto Microcomputer Co. KZM-A9-Dual
21 - const: renesas,emev2
23 - description: RZ/A1H (R7S72100)
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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dwkup_m3_rproc.txt1 TI Wakeup M3 Remoteproc Driver
4 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
5 (commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
10 Wkup M3 Device Node:
12 A wkup_m3 device node is used to represent the Wakeup M3 processor instance
17 --------------------
18 - compatible: Should be one of,
19 "ti,am3352-wkup-m3" for AM33xx SoCs
20 "ti,am4372-wkup-m3" for AM43xx SoCs
21 - reg: Should contain the address ranges for the two internal
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H A Dqcom,rpm-proc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,rpm-proc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konrad.dybcio@linaro.org>
12 - Stephan Gerhold <stephan@gerhold.net>
17 +--------------------------------------------+
18 | RPM subsystem (qcom,rpm-proc) |
20 reset | +---------------+ +-----+ +-----+ |
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/openbmc/u-boot/doc/
H A DREADME.rmobile4 This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1]
5 and Cortex-A9/A53/A57 based R-Car[2] family of SoCs. Renesas's RMOBILE/R-Car SoC
6 family contains an ARM Cortex-A9/A53/A57.
12 | R8A73A0 | KMC KZM-A9-GT [3] | kzm9g_config
13 | R8A7734 | Atmark-Techno Armadillo-800-EVA [4] | armadillo-800eva_config
17 |---------------+----------------------------------------+-------------------
18 | R8A7791 M2-W | Renesas Electronics Koelsch | koelsch_defconfig
20 |---------------+----------------------------------------+-------------------
22 |---------------+----------------------------------------+-------------------
23 | R8A7793 M2-N | Renesas Electronics Gose | gose_defconfig
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/openbmc/linux/arch/arm/mm/
H A Dproc-v7m.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7m.S
8 * This is the "shell" of the ARMv7-M processor support.
14 #include "proc-macros.S"
31 * - loc - location to jump to for soft reset
104 * This should be able to cover all ARMv7-M cores.
140 ldmia sp, {r0-r3, r12}
144 @ Special-purpose control register
150 stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
152 teq r8, #0 @ re-evalutae condition
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/openbmc/u-boot/arch/arm/mach-rockchip/rk3288/
H A DKconfig4 bool "Google/Rockchip Veyron-Jerry Chromebook"
7 Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports,
8 HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and
9 WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
13 bool "Google/Rockchip Veyron-Mickey Chromebit"
16 Mickey is a small RK3288-based device with one USB 3.0 port, HDMI
23 bool "Google/Rockchip Veyron-Minnie Chromebook"
26 Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0
27 ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card,
29 EC (Cortex-M3) to provide access to the keyboard and battery
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/openbmc/openbmc/meta-arm/meta-arm-bsp/conf/machine/
H A Dcorstone1000-fvp.conf2 #@NAME: corstone1000-fvp machine
3 #@DESCRIPTION: Machine configuration for Corstone1000 64-bit FVP
16 FVP_PROVIDER ?= "fvp-corstone1000-native"
17 FVP_EXE ?= "FVP_Corstone-1000"
19 FVP_CONSOLES[tf-a] = "host_terminal_1"
42 FVP_DATA ?= "board.flash0=corstone1000-flash-firmware-image-${MACHINE}.wic@0x68000000"
44 # External system (cortex-M3)
51 FVP_TERMINALS[extsys0.extsys_terminal] ?= "Cortex M3"
69 FVP_CONFIG[board.msd_mmc_2.p_mmc_file] ?= "corstone1000-esp-image-${MACHINE}.wic"
71 # Virtio-Net configuration
/openbmc/linux/drivers/soc/ti/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
18 Packets are queued/de-queued by writing/reading descriptor address
40 c-states on AM335x. Also required for rtc and ddr in self-refresh low
44 tristate "TI AMx3 Wkup-M3 IPC Driver"
48 TI AM33XX and AM43XX have a Cortex M3, the Wakeup M3, to handle
50 to communicate and use the Wakeup M3 for PM features like suspend
87 tristate "TI PRU-ICSS Subsystem Platform drivers"
91 TI PRU-ICSS Subsystem platform specific support.
/openbmc/u-boot/arch/arm/cpu/armv7m/
H A Dsystick-timer.c1 // SPDX-License-Identifier: GPL-2.0+
3 * ARM Cortex M3/M4/M7 SysTick timer driver
6 * Based on arch/arm/mach-stm32/stm32f1/timer.c
13 * The SysTick timer is a 24-bit count down timer. The clock can be either the
29 /* SysTick Base Address - fixed for all Cortex M3, M4 and M7 devices */
47 /* read the 24-bit timer */
53 return TIMER_MAX_VAL - readl(&systick->current_val); in read_timer()
61 writel(TIMER_MAX_VAL, &systick->reload_val); in timer_init()
63 writel(0, &systick->current_val); in timer_init()
65 cal = readl(&systick->calibration); in timer_init()
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/openbmc/linux/Documentation/devicetree/bindings/soc/ti/
H A Dwkup-m3-ipc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/ti/wkup-m3-ipc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Wakeup M3 IPC device
10 - Dave Gerlach <d-gerlach@ti.com>
11 - Drew Fustini <dfustini@baylibre.com>
14 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
15 (commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
17 C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dcpu-v7m.c2 * QEMU ARMv7-M TCG-only CPUs.
8 * SPDX-License-Identifier: GPL-2.0-or-later
13 #include "accel/tcg/cpu-ops.h"
23 CPUARMState *env = &cpu->env; in arm_v7m_cpu_exec_interrupt()
27 * ARMv7-M interrupt masking works differently than -A or -R. in arm_v7m_cpu_exec_interrupt()
35 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { in arm_v7m_cpu_exec_interrupt()
36 cs->exception_index = EXCP_IRQ; in arm_v7m_cpu_exec_interrupt()
37 cs->cc->tcg_ops->do_interrupt(cs); in arm_v7m_cpu_exec_interrupt()
48 set_feature(&cpu->env, ARM_FEATURE_V6); in cortex_m0_initfn()
49 set_feature(&cpu->env, ARM_FEATURE_M); in cortex_m0_initfn()
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/openbmc/linux/arch/arm/mach-versatile/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
52 bool "Include support for Integrator/IM-PD1"
60 The IM-PD1 is an add-on logic module for the Integrator which
62 The IM-PD1 can be found on the Integrator/PP2 platform.
77 bool "Integrator/CM922T-XA10 core module"
83 bool "Integrator/CM926EJ-S core module"
107 bool "Integrator/CM1026EJ-S core module"
113 bool "Integrator/CM1136JF-S core module"
129 bool "Integrator/CT926 (ARM926EJ-S) core tile"
135 bool "Integrator/CTB36 (ARM1136JF-S) core tile"
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/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Dxgene-slimpro-mailbox.txt1 The APM X-Gene SLIMpro mailbox is used to communicate messages between
2 the ARM64 processors and the Cortex M3 (dubbed SLIMpro). It uses a simple
10 - compatible: Should be as "apm,xgene-slimpro-mbox".
12 - reg: Contains the mailbox register address range.
14 - interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the
18 - #mbox-cells: only one to specify the mailbox channel number.
24 compatible = "apm,xgene-slimpro-mbox";
26 #mbox-cells = <1>;
/openbmc/openbmc/poky/meta/conf/machine/include/arm/
H A Dfeature-arm-thumb.inc22 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'thumb', ' -m${ARM_M_OPT}', '', d)}"
32 # what about armv7m devices which don't support -marm (e.g. Cortex-M3)?
33 TARGET_CC_KERNEL_ARCH += "${@bb.utils.contains('TUNE_FEATURES', 'thumb', '-mno-thumb-interwork -mar…
/openbmc/qemu/include/hw/arm/
H A Dmsf2-soc.h29 #include "hw/timer/mss-timer.h"
30 #include "hw/misc/msf2-sysreg.h"
31 #include "hw/ssi/mss-spi.h"
32 #include "hw/net/msf2-emac.h"
36 #define TYPE_MSF2_SOC "msf2-soc"
43 * System timer consists of two programmable 32-bit
45 * the Cortex-M3 processor
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/external-system/
H A Dexternal-system_0.1.0.bb1 SUMMARY = "External system Cortex-M3 Firmware"
4 HOMEPAGE = "https://git.linaro.org/landing-teams/working/arm/external-system.git"
5 DEPENDS = "gcc-arm-none-eabi-native"
7 LICENSE = "BSD-3-Clause & Apache-2.0"
11 SRC_URI = "gitsm://git.gitlab.arm.com/arm-reference-solutions/corstone1000/external_system/rtx.git;…
12 file://0001-tools-gen_module_code-atomically-rewrite-the-generat.patch"
20 PRODUCT = "corstone-1000"
25 # remove once arm-none-eabi-gcc updates to 13 or newer like poky
26 DEBUG_PREFIX_MAP:remove = "-fcanon-prefix-map"
31 oe_runmake -C ${S} V=y \
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/openbmc/u-boot/arch/arm/mach-rockchip/rk3399/
H A DKconfig10 with full function and phisical connectors support like type-C ports,
11 usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
14 bool "Theobroma Systems RK3399-Q7 (Puma)"
16 The RK3399-Q7 (Puma) is a system-on-module (designed and
18 in a Qseven-compatible form-factor (running of a single 5V
19 supply and exposing its external interfaces on a MXM-230
22 Key features of the RK3399-Q7 include:
23 * on-module USB 3.0 hub (2x USB 3.0 host + 1x USB 2.0 host)
24 * USB 3.0 dual-role
25 * on-module Micrel KSZ9031 GbE PHY
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