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/openbmc/linux/arch/x86/kernel/cpu/
H A Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0
60 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
61 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
62 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
63 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
64 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
65 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
66 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
67 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
68 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
[all …]
H A Dintel.c1 // SPDX-License-Identifier: GPL-2.0
22 #include <asm/intel-family.h>
67 * Processors which have self-snooping capability can handle conflicting
75 switch (c->x86_vfm) { in check_memory_type_self_snoop_errata()
107 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
109 switch (c->x86_vfm) { in probe_xeon_phi_r3mwait()
131 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
132 * - https://kb.vmware.com/s/article/52345
133 * - Microcode revisions observed in the wild
134 * - Release note from 20180108 microcode release
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/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-matmap.h2 * xtensa/config/core-matmap.h -- Memory access and translation mapping
10 * information contained in the core-isa.h header file.
19 * XCHAL_ICACHE_SIZE (presence of I-cache)
20 * XCHAL_DCACHE_SIZE (presence of D-cache)
25 /* Copyright (c) 1999-2020 Tensilica Inc.
49 /*----------------------------------------------------------------------
51 ----------------------------------------------------------------------*/
55 /* Cache Attribute encodings -- lists of access modes for each cache attribute: */
117 #define XCHAL_CA_WRITETHRU 11 /* cache enabled (write-through) mode */
118 #define XCHAL_CA_WRITEBACK 7 /* cache enabled (write-back) mode */
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/openbmc/linux/arch/mips/kernel/
H A Dbmips_5xxx_init.S7 * Copyright (C) 2011-2012 by Broadcom Corporation
34 addiu t1, t1, -1 ; \
87 #define BRCM_ZSC_RBUS_ADDR_MAPPING_REG2 8 << 3
112 * Description: compute the I-cache size and I-cache line size
126 * Determine sets per way: IS
128 * This field contains the number of sets (i.e., indices) per way of
131 * vi) 0x5 - 0x7: Reserved.
137 /* sets per way = (64<<IS) */
146 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
164 /* v0 now have sets per way, multiply it by line size now
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/openbmc/u-boot/doc/
H A DREADME.N12137 - 16-/32-bit mixable instruction format.
8 - 32 general-purpose 32-bit registers.
9 - 8-stage pipeline.
10 - Dynamic branch prediction.
11 - 32/64/128/256 BTB.
12 - Return address stack (RAS).
13 - Vector interrupts for internal/external.
15 - 3 HW-level nested interruptions.
16 - User and super-user mode support.
17 - Memory-mapped I/O.
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/openbmc/linux/arch/arm/mm/
H A Dcache-xsc3l2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-xsc3l2.c - XScale3 L2 cache controller support
17 #define CACHE_WAY_PER_SET 8
19 #define CACHE_WAY_SIZE(l2ctype) (8192 << (((l2ctype) >> 8) & 0xf))
44 int set, way; in xsc3_l2_inv_all() local
49 for (way = 0; way < CACHE_WAY_PER_SET; way++) { in xsc3_l2_inv_all()
50 set_way = (way << 29) | (set << 5); in xsc3_l2_inv_all()
61 if (va != -1) in l2_unmap_va()
70 unsigned long pa_offset = pa << (32 - PAGE_SHIFT); in l2_map_va()
71 if (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) { in l2_map_va()
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/openbmc/linux/arch/openrisc/include/asm/
H A Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
35 #define SPRGROUP_PM (8 << MAX_SPRS_PER_GRP_BITS)
49 #define SPR_PCCFGR (SPRGROUP_SYS + 8)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) argument
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) argument
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) argument
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) argument
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) argument
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/openbmc/linux/Documentation/arch/x86/
H A Dentry_64.rst1 .. SPDX-License-Identifier: GPL-2.0
16 for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally
17 arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility
18 syscall entry points and thus provides for 32-bit processes the
19 ability to execute syscalls when running on 64-bit kernels.
25 - system_call: syscall instruction from 64-bit code.
27 - entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall
28 either way.
30 - entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit
33 - interrupt: An array of entries. Every IDT vector that doesn't
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/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2836.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "bcm2835-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 local_intc: interrupt-controller@40000000 {
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a7-pmu";
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/openbmc/linux/Documentation/admin-guide/
H A Ddevices.txt1 0 Unnamed devices (e.g. non-device mounts)
7 2 = /dev/kmem OBSOLETE - replaced by /proc/kcore
11 6 = /dev/core OBSOLETE - replaced by /proc/kcore
13 8 = /dev/random Nondeterministic random number gen.
18 12 = /dev/oldmem OBSOLETE - replaced by /proc/vmcore
31 2 char Pseudo-TTY masters
37 Pseudo-tty's are named as follows:
40 the 1st through 16th series of 16 pseudo-ttys each, and
44 These are the old-style (BSD) PTY devices; Unix98
67 8 = /dev/fd?h1200 5.25" 1200K in a 1200K drive(1)
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/openbmc/linux/arch/mips/mm/
H A Dcerr-sb1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.)
73 printk(" multiple-buserr"); in breakout_errctl()
80 printk(" tag-parity"); in breakout_cerri()
82 printk(" data-parity"); in breakout_cerri()
114 printk(" multi-err"); in breakout_cerrd()
116 printk(" tag-state"); in breakout_cerrd()
118 printk(" tag-address"); in breakout_cerrd()
120 printk(" data-SBE"); in breakout_cerrd()
122 printk(" data-DBE"); in breakout_cerrd()
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/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-matmap.h2 * xtensa/config/core-matmap.h -- Memory access and translation mapping
10 * information contained in the core-isa.h header file.
19 * XCHAL_ICACHE_SIZE (presence of I-cache)
20 * XCHAL_DCACHE_SIZE (presence of D-cache)
25 /* Copyright (c) 1999-2010 Tensilica Inc.
49 /*----------------------------------------------------------------------
51 ----------------------------------------------------------------------*/
54 /* Cache Attribute encodings -- lists of access modes for each cache attribute: */
112 #define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */
113 #define XCHAL_CA_WRITEBACK 4 /* cache enabled (write-back) mode */
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/openbmc/linux/arch/arm/include/asm/
H A Dv7m.h1 /* SPDX-License-Identifier: GPL-2.0 */
49 * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
50 * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
62 /* Memory-mapped MPU registers for M-class */
75 #define PMSAv8_RBAR_A(n) (PMSAv8_RBAR + 8*(n))
76 #define PMSAv8_RLAR_A(n) (PMSAv8_RLAR + 8*(n))
81 #define V7M_SCB_ICIALLU 0x250 /* I-cache invalidate all to PoU */
82 #define V7M_SCB_ICIMVAU 0x258 /* I-cache invalidate by MVA to PoU */
83 #define V7M_SCB_DCIMVAC 0x25c /* D-cache invalidate by MVA to PoC */
84 #define V7M_SCB_DCISW 0x260 /* D-cache invalidate by set-way */
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H A Duser.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 /* Core file format: The core file is written in such a way that gdb
9 linux we use the 'trad-core' bfd). There are quite a number of
21 DATA: The data area is stored. We use current->end_text to
22 current->brk to pick up all of the user variables, plus any memory
24 is demand-zero or if a page is totally unused, we just cover the entire
25 range. All of the addresses are rounded in such a way that an integral
29 current->start_stack, so we round each of these off in order to be able
43 } fpregs[8];
46 unsigned char ftype[8];
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/openbmc/linux/arch/arc/mm/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
26 * Utility Routine to erase a J-TLB entry
89 * with existing location. This will cause Write CMD to over-write in tlb_entry_insert()
131 * Un-conditionally (without lookup) erase the entire MMU contents
139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
175 * Flush the entire MM for userland. The fastest way is to move to Next ASID
185 if (atomic_read(&mm->mm_users) == 0) in local_flush_tlb_mm()
189 * - Move to a new ASID, but only if the mm is still wired in in local_flush_tlb_mm()
190 * (Android Binder ended up calling this for vma->mm != tsk->mm, in local_flush_tlb_mm()
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/openbmc/linux/arch/x86/crypto/
H A Dblowfish-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 .file "blowfish-x86_64-asm.S"
57 * 1-way blowfish
83 movq p+4*(n-1)(CTX), RT0; \
120 round_enc(8);
166 4-way blowfish, four blocks parallel
169 /* F() for 4-way. Slower when used alone/1-way, but faster when used
170 * parallel/4-way (tested on AMD Phenom II & Intel Xeon E7330).
212 movq p+4*((n)-1)(CTX), RKEY; \
217 preload_roundkey_dec(n - 2);
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/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-l2c.h7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
44 #define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
52 /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
78 CVMX_L2C_EVENT_INDEX_CONFLICT = 8,
137 CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB = 8,
183 * Return the L2 Cache way partitioning for a given core.
189 * -1 on error
199 * a way, while a 1 bit blocks the core from evicting any
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/openbmc/qemu/target/xtensa/
H A Dmmu_helper.c2 * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab.
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 #include "qemu/qemu-print.h"
33 #include "exec/helper-proto.h"
34 #include "qemu/host-utils.h"
35 #include "exec/exec-all.h"
36 #include "exec/page-protection.h"
40 #define XTENSA_MPU_ACC_RIGHTS_SHIFT 8
67 * only the side-effects (ie any MMU or other exception) in HELPER()
76 if (v != env->sregs[RASID]) { in HELPER()
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/openbmc/u-boot/board/cadence/xtfpga/
H A DREADME8 - XT-AV60 / LX60
9 - XT-AV110 / LX110
10 - XT-AV200 / LX200
11 - ML605
12 - KC705
16 - An Xtensa or Diamond processor core.
17 - An on-chip-debug (OCD) JTAG interface.
18 - A 16550 compatible UART and serial port.
19 - An OpenCores Wishbone 10/100-base-T ethernet interface.
20 - A 32 char two line LCD display. (except for the LX200)
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/openbmc/linux/arch/x86/include/asm/
H A Duser_32.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Core file format: The core file is written in such a way that gdb
8 linux we use the 'trad-core' bfd). There are quite a number of
20 DATA: The data area is stored. We use current->end_text to
21 current->brk to pick up all of the user variables, plus any memory
23 is demand-zero or if a page is totally unused, we just cover the entire
24 range. All of the addresses are rounded in such a way that an integral
28 current->start_stack, so we round each of these off in order to be able
38 * interacting with the FXSR-format floating point environment. Floating
53 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
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/openbmc/linux/arch/ia64/lib/
H A Dstrlen.S1 /* SPDX-License-Identifier: GPL-2.0 */
14 * Copyright (C) 1999, 2001 Hewlett-Packard Co
30 // The goal is to look at the string in chunks of 8 bytes.
32 // string may not be 8-byte aligned. In this case we load the 8byte
36 // latency and do read ahead safely. This way we defer any exception.
55 // - the cmp r0,r0 is used as a fast way to initialize a predicate
59 // - we don't use the epilogue counter to exit the loop but we need to set
62 // - after the loop we must test for Nat values because neither the
68 // - Clearly performance tuning is required.
86 alloc saved_pfs=ar.pfs,11,0,0,8 // rotating must be multiple of 8
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/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dmp.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2011 Freescale Semiconductor, Inc.
27 * Determine if U-Boot should keep secondary cores in reset, or let them out
48 out_be32(&pic->pir, 1 << nr); in cpu_reset()
50 (void)in_be32(&pic->pir); in cpu_reset()
51 out_be32(&pic->pir, 0x0); in cpu_reset()
73 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]); in cpu_status()
74 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]); in cpu_status()
75 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); in cpu_status()
86 setbits_be32(&gur->coredisrl, 1 << nr); in cpu_disable()
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/openbmc/linux/arch/powerpc/mm/nohash/
H A Dtlb_low.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low-level functions for performing various
7 * This file implements the following functions for all no-hash
11 * - tlbil_va
12 * - tlbil_pid
13 * - tlbil_all
14 * - tlbivax_bcast
18 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
29 #include <asm/asm-offsets.h>
32 #include <asm/asm-compat.h>
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/openbmc/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-l2c.c7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36 #include <asm/octeon/cvmx-l2c.h>
37 #include <asm/octeon/cvmx-spinlock.h>
43 * NOTE: This only protects calls from within a single application -
55 return -1; in cvmx_l2c_get_core_way_partition()
64 field = (core & 0x3) * 8; in cvmx_l2c_get_core_way_partition()
89 valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1; in cvmx_l2c_set_core_way_partition()
95 return -1; in cvmx_l2c_set_core_way_partition()
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/openbmc/qemu/docs/specs/
H A Divshmem-spec.rst2 Device Specification for Inter-VM shared memory device
5 The Inter-VM shared memory device (ivshmem) is designed to share a
27 --------
31 - BAR0 holds device registers (256 Byte MMIO)
32 - BAR1 holds MSI-X table and PBA (only ivshmem-doorbell)
33 - BAR2 maps the shared memory object
37 - If you only need the shared memory part, BAR2 suffices. This way,
41 - If you additionally need the capability for peers to interrupt each
50 IVPosition register (described below) to become non-negative before
57 --------------------
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