1*afc1ce82SMacpaul LinN1213 is a configurable hard/soft core of NDS32's N12 CPU family. 2*afc1ce82SMacpaul Lin 3*afc1ce82SMacpaul LinFeatures 4*afc1ce82SMacpaul Lin======== 5*afc1ce82SMacpaul Lin 6*afc1ce82SMacpaul LinCPU Core 7*afc1ce82SMacpaul Lin - 16-/32-bit mixable instruction format. 8*afc1ce82SMacpaul Lin - 32 general-purpose 32-bit registers. 9*afc1ce82SMacpaul Lin - 8-stage pipeline. 10*afc1ce82SMacpaul Lin - Dynamic branch prediction. 11*afc1ce82SMacpaul Lin - 32/64/128/256 BTB. 12*afc1ce82SMacpaul Lin - Return address stack (RAS). 13*afc1ce82SMacpaul Lin - Vector interrupts for internal/external. 14*afc1ce82SMacpaul Lin interrupt controller with 6 hardware interrupt signals. 15*afc1ce82SMacpaul Lin - 3 HW-level nested interruptions. 16*afc1ce82SMacpaul Lin - User and super-user mode support. 17*afc1ce82SMacpaul Lin - Memory-mapped I/O. 18*afc1ce82SMacpaul Lin - Address space up to 4GB. 19*afc1ce82SMacpaul Lin 20*afc1ce82SMacpaul LinMemory Management Unit 21*afc1ce82SMacpaul Lin - TLB 22*afc1ce82SMacpaul Lin - 4/8-entry fully associative iTLB/dTLB. 23*afc1ce82SMacpaul Lin - 32/64/128-entry 4-way set-associati.ve main TLB. 24*afc1ce82SMacpaul Lin - TLB locking support 25*afc1ce82SMacpaul Lin - Optional hardware page table walker. 26*afc1ce82SMacpaul Lin - Two groups of page size support. 27*afc1ce82SMacpaul Lin - 4KB & 1MB. 28*afc1ce82SMacpaul Lin - 8KB & 1MB. 29*afc1ce82SMacpaul Lin 30*afc1ce82SMacpaul LinMemory Subsystem 31*afc1ce82SMacpaul Lin - I & D cache. 32*afc1ce82SMacpaul Lin - Virtually indexed and physically tagged. 33*afc1ce82SMacpaul Lin - Cache size: 8KB/16KB/32KB/64KB. 34*afc1ce82SMacpaul Lin - Cache line size: 16B/32B. 35*afc1ce82SMacpaul Lin - Set associativity: 2-way, 4-way or direct-mapped. 36*afc1ce82SMacpaul Lin - Cache locking support. 37*afc1ce82SMacpaul Lin - I & D local memory (LM). 38*afc1ce82SMacpaul Lin - Size: 4KB to 1MB. 39*afc1ce82SMacpaul Lin - Bank numbers: 1 or 2. 40*afc1ce82SMacpaul Lin - Optional 1D/2D DMA engine. 41*afc1ce82SMacpaul Lin - Internal or external to CPU core. 42*afc1ce82SMacpaul Lin 43*afc1ce82SMacpaul LinBus Interface 44*afc1ce82SMacpaul Lin - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports. 45*afc1ce82SMacpaul Lin - Synchronous High speed memory port. 46*afc1ce82SMacpaul Lin (HSMP): 0, 1 or 2 ports. 47*afc1ce82SMacpaul Lin 48*afc1ce82SMacpaul LinDebug 49*afc1ce82SMacpaul Lin - JTAG debug interface. 50*afc1ce82SMacpaul Lin - Embedded debug module (EDM). 51*afc1ce82SMacpaul Lin - Optional embedded program tracer interface. 52*afc1ce82SMacpaul Lin 53*afc1ce82SMacpaul LinMiscellaneous 54*afc1ce82SMacpaul Lin - Programmable data endian control. 55*afc1ce82SMacpaul Lin - Performance monitoring mechanism. 56