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/openbmc/linux/include/linux/mfd/
H A Dmax5970.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define MAX5970_NUM_LEDS 4
31 #define MAX5970_REG_CURRENT_L(ch) (0x01 + (ch) * 4) argument
32 #define MAX5970_REG_CURRENT_H(ch) (0x00 + (ch) * 4) argument
33 #define MAX5970_REG_VOLTAGE_L(ch) (0x03 + (ch) * 4) argument
34 #define MAX5970_REG_VOLTAGE_H(ch) (0x02 + (ch) * 4) argument
37 #define MAX5970_MON(reg, ch) (((reg) >> ((ch) * 2)) & MAX5970_MON_MASK) argument
40 #define MAX5970_REG_CH_UV_WARN_H(ch) (0x1A + (ch) * 10) argument
41 #define MAX5970_REG_CH_UV_WARN_L(ch) (0x1B + (ch) * 10) argument
42 #define MAX5970_REG_CH_UV_CRIT_H(ch) (0x1C + (ch) * 10) argument
[all …]
H A Drz-mtu3.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* 8-bit shared register offsets macros */
16 /* 16-bit shared register offset macros */
31 /* 8-bit register offset macros of MTU3 channels except MTU5 */
36 #define RZ_MTU3_TCR2 4 /* Timer control register 2 */
47 /* Only MTU3/4/6/7 have TBTM registers */
50 /* 8-bit MTU5 register offset macros */
53 #define RZ_MTU3_TCRU 4 /* Timer control register U */
63 /* 16-bit register offset macros of MTU3 channels except MTU5 */
68 #define RZ_MTU3_TGRD 4 /* Timer general register D */
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/openbmc/qemu/hw/dma/
H A Dsifive_pdma.c28 #include "hw/qdev-properties.h"
71 static void sifive_pdma_run(SiFivePDMAState *s, int ch) in sifive_pdma_run() argument
73 uint64_t bytes = s->chan[ch].next_bytes; in sifive_pdma_run()
74 uint64_t dst = s->chan[ch].next_dst; in sifive_pdma_run()
75 uint64_t src = s->chan[ch].next_src; in sifive_pdma_run()
76 uint32_t config = s->chan[ch].next_config; in sifive_pdma_run()
112 s->chan[ch].state = DMA_CHAN_STATE_STARTED; in sifive_pdma_run()
113 s->chan[ch].control &= ~CONTROL_DONE; in sifive_pdma_run()
114 s->chan[ch].control &= ~CONTROL_ERR; in sifive_pdma_run()
117 s->chan[ch].exec_config = config; in sifive_pdma_run()
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H A Dbcm2835_dma.c5 * See the COPYING file in the top-level directory.
20 #define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */
30 #define BCM2708_DMA_D_INC (1 << 4)
42 /* the current control block appears in the following registers - read only */
58 BCM2835DMAChan *ch = &s->chan[c]; in bcm2835_dma_update() local
62 if (!(s->enable & (1 << c))) { in bcm2835_dma_update()
66 while ((s->enable & (1 << c)) && (ch->conblk_ad != 0)) { in bcm2835_dma_update()
68 ch->ti = ldl_le_phys(&s->dma_as, ch->conblk_ad); in bcm2835_dma_update()
69 ch->source_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 4); in bcm2835_dma_update()
70 ch->dest_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 8); in bcm2835_dma_update()
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H A Dpl330.c20 #include "hw/qdev-properties.h"
41 #define PL330_FIFO_ERR (-1)
45 #define PL330_FAULT_DMAGO_ERR (1 << 4)
89 #define CFG_PNS 4
104 pl330_chan_waiting_event = 4,
238 #define PERIPH_SEC_STATE 4
325 len = MIN(16, size - b); in pl330_hexdump()
327 qemu_hexdump_line(str, buf + b, len, 1, 4); in pl330_hexdump()
328 trace_pl330_hexdump(b, str->str); in pl330_hexdump()
335 * stored in this buffer. Data is stored in BUF field, tags - in the
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H A Domap_dma.c4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br>
110 qemu_irq irq[4];
118 uint32_t irqen[4];
119 uint32_t irqstat[4];
122 struct omap_dma_channel_s ch[32]; member
131 #define LAST_FRAME_INTR (1 << 4)
140 s->intr_update(s); in omap_dma_interrupts_update()
143 static void omap_dma_channel_load(struct omap_dma_channel_s *ch) in omap_dma_channel_load() argument
145 struct omap_dma_reg_set_s *a = &ch->active_set; in omap_dma_channel_load()
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/openbmc/linux/drivers/gpu/drm/imx/dcss/
H A Ddcss-scaler.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "dcss-dev.h"
15 #define REPEAT_EN BIT(4)
32 #define Y_UV_BYTE_SWAP BIT(4)
38 #define CHR_BIT_DEPTH_POS 4
39 #define CHR_BIT_DEPTH_MASK GENMASK(5, 4)
90 struct dcss_scaler_ch ch[3]; member
96 #define PSC_BITS_FOR_PHASE 4
103 #define PSC_PHASE_MASK (PSC_NUM_PHASES - 1)
105 #define PSC_Q_ROUND_OFFSET (1 << (PSC_Q_FRACTION - 1))
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H A Ddcss-dpr.c1 // SPDX-License-Identifier: GPL-2.0
9 #include "dcss-dev.h"
16 #define SW_SHADOW_LOAD_SEL BIT(4)
25 #define DPR2RTR_YRGB_FIFO_OVFL BIT(4)
33 #define TILE_TYPE_MASK GENMASK(4, 2)
53 #define ROT_FLIP_ORDER_EN BIT(4)
73 #define THRES_LOW_POS 4
74 #define THRES_LOW_MASK GENMASK(6, 4)
118 struct dcss_dpr_ch ch[3]; member
121 static void dcss_dpr_write(struct dcss_dpr_ch *ch, u32 val, u32 ofs) in dcss_dpr_write() argument
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/openbmc/linux/drivers/clk/berlin/
H A Dberlin2-avpll.c1 // SPDX-License-Identifier: GPL-2.0
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 #include <linux/clk-provider.h>
15 #include "berlin2-avpll.h"
19 * VCO with 8 channels each, channel 8 is the odd-one-out and does
34 /* BG2/BG2CDs VCO_B has an additional shift of 4 for its VCO_CTRL0 reg */
67 #define VCO_SPEED_1G86_2G00 VCO_SPEED(4)
118 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
119 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_is_enabled()
120 reg >>= 4; in berlin2_avpll_vco_is_enabled()
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/openbmc/linux/drivers/clocksource/
H A Dsh_mtu2.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - MTU2
55 #define TSTR -1 /* shared register */
60 #define TSR 4 /* channel register */
75 /* Values 4 to 7 are channel-dependent */
80 #define TCR_TPSC_CH0_TCLKA (4 << 0)
84 #define TCR_TPSC_CH1_TCLKA (4 << 0)
88 #define TCR_TPSC_CH2_TCLKA (4 << 0)
92 #define TCR_TPSC_CH34_P256 (4 << 0)
100 #define TMDR_BFA (1 << 4)
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H A Dsh_tmu.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - TMU
70 #define TSTR -1 /* shared register */
81 #define TCR_TPSC_CLK1024 (4 << 0)
84 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr) in sh_tmu_read() argument
89 switch (ch->tmu->model) { in sh_tmu_read()
91 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
93 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
100 return ioread16(ch->base + offs); in sh_tmu_read()
102 return ioread32(ch->base + offs); in sh_tmu_read()
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/openbmc/linux/drivers/gpu/ipu-v3/
H A Dipu-prv.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
17 #include <video/imx-ipu-v3.h>
53 #define IPU_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0150 + 4 * ((ch) / 32)) argument
54 #define IPU_ALT_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0168 + 4 * ((ch) / 32)) argument
55 #define IPU_CHA_CUR_BUF(ch) IPU_CM_REG(0x023C + 4 * ((ch) / 32)) argument
61 #define IPU_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0268 + 4 * ((ch) / 32)) argument
62 #define IPU_CHA_BUF1_RDY(ch) IPU_CM_REG(0x0270 + 4 * ((ch) / 32)) argument
63 #define IPU_CHA_BUF2_RDY(ch) IPU_CM_REG(0x0288 + 4 * ((ch) / 32)) argument
64 #define IPU_ALT_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0278 + 4 * ((ch) / 32)) argument
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H A Dipu-cpmem.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
11 #include "ipu-prv.h"
34 #define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4)
74 #define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4)
93 ipu_get_cpmem(struct ipuv3_channel *ch) in ipu_get_cpmem() argument
95 struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv; in ipu_get_cpmem()
97 return cpmem->base + ch->num; in ipu_get_cpmem()
100 static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v) in ipu_ch_param_write_field() argument
102 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); in ipu_ch_param_write_field()
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/openbmc/linux/drivers/staging/most/dim2/
H A Dhal.c1 // SPDX-License-Identifier: GPL-2.0
3 * hal.c - DIM2 HAL implementation
6 * Copyright (C) 2015-2016, Microchip Technology Germany II GmbH & Co. KG
25 * Number of 32-bit units for DBR map.
29 * 4: block size is 128, max allocation is 4K
37 /* -------------------------------------------------------------------------- */
50 /* -------------------------------------------------------------------------- */
64 /* -------------------------------------------------------------------------- */
86 /* -------------------------------------------------------------------------- */
99 * alloc_dbr() - Allocates DBR memory.
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/openbmc/linux/drivers/dma/
H A Dmoxart-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
28 #include "virt-dma.h"
30 #define APB_DMA_MAX_CHANNEL 4
33 #define REG_OFF_ADDRESS_DEST 4
42 #define APB_DMA_ERR_INT_STS BIT(4)
60 * 001: +1 (Burst=0), +4 (Burst=1)
62 * 011: +4 (Burst=0), +16 (Burst=1)
63 * 101: -1 (Burst=0), -4 (Burst=1)
64 * 110: -2 (Burst=0), -8 (Burst=1)
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/openbmc/qemu/hw/char/
H A Dipoctal232.c2 * QEMU GE IP-Octal 232 IndustryPack emulation
14 #include "hw/qdev-properties.h"
15 #include "hw/qdev-properties-system.h"
19 #include "chardev/char-fe.h"
31 #define DPRINTF(fmt, ...) DPRINTF2("IP-Octal: " fmt, ## __VA_ARGS__)
35 /* The IP-Octal has 8 channels (a-h)
36 divided into 4 blocks (A-D) */
38 #define N_BLOCKS 4
61 #define CR_CMD(cr) ((cr) >> 4)
66 #define CR_RESET_ERR 4
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/openbmc/linux/lib/
H A Dhexdump.c1 // SPDX-License-Identifier: GPL-2.0-only
20 * hex_to_bin - convert a hex digit to its real value
21 * @ch: ascii character represents hex digit
23 * hex_to_bin() converts one hex digit to its actual value or -1 in case of bad
30 * (ch - '9' - 1) is negative if ch <= '9'
31 * ('0' - 1 - ch) is negative if ch >= '0'
32 * we "and" these two values, so the result is negative if ch is in the range
35 * shift of a negative value is implementation-defined, so we cast the
36 * value to (unsigned) before the shift --- we have 0xffffff if ch is in
38 * we "and" this value with (ch - '0' + 1) --- we have a value 1 ... 10 if ch is
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/openbmc/u-boot/lib/
H A Dtiny-printf.c1 // SPDX-License-Identifier: LGPL-2.1+
18 char zs; /* non-zero if a digit has been written */
22 void (*putc)(struct printf_info *info, char ch);
27 *info->bf++ = c; in out()
32 out(info, dgt + (dgt < 10 ? '0' : 'a' - 10)); in out_dgt()
33 info->zs = 1; in out_dgt()
42 *num -= div; in div_out()
46 if (info->zs || dgt > 0) in div_out()
53 char ch; in string() local
55 while ((ch = *s++)) in string()
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/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Des-Huesca1 # DVB-T Huesca (Aragon) [Spain] [es-Huesca]
3 #------------------------------------------------------------------------------
5 [CH 43 HTV-HuescaTelevision]
13 GUARD_INTERVAL = 1/4
17 [CH 44 La Sexta 2]
25 GUARD_INTERVAL = 1/4
29 [CH 45 TVE HD]
37 GUARD_INTERVAL = 1/4
41 [CH 48 NITRO]
49 GUARD_INTERVAL = 1/4
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/openbmc/u-boot/arch/x86/cpu/quark/
H A Dsmc.c1 // SPDX-License-Identifier: Intel
82 tck = t_ck[mrc_params->ddr_speed]; /* Clock in picoseconds */ in prog_ddr_timing_control()
83 tcl = mrc_params->params.cl; /* CAS latency in clocks */ in prog_ddr_timing_control()
86 tras = MCEIL(mrc_params->params.ras, tck); in prog_ddr_timing_control()
88 /* Per JEDEC: tWR=15000ps DDR2/3 from 800-1600 */ in prog_ddr_timing_control()
91 twtr = MCEIL(mrc_params->params.wtr, tck); in prog_ddr_timing_control()
92 trrd = MCEIL(mrc_params->params.rrd, tck); in prog_ddr_timing_control()
93 trtp = 4; /* Valid for 800 and 1066, use 5 for 1333 */ in prog_ddr_timing_control()
94 tfaw = MCEIL(mrc_params->params.faw, tck); in prog_ddr_timing_control()
96 wl = 5 + mrc_params->ddr_speed; in prog_ddr_timing_control()
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/openbmc/linux/arch/x86/crypto/
H A Dsha256-avx2-asm.S2 # Implement fast SHA-256 with AVX2 instructions. (x86_64)
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
41 # This code is described in an Intel White-Paper:
42 # "Fast SHA-256 Implementations on Intel Architecture Processors"
48 # This code schedules 2 blocks at a time, with 4 lanes per block
60 # Add reg to mem using reg-mem add and store
87 SHUF_00BA = %ymm10 # shuffle xBxA -> 00BA
88 SHUF_DC00 = %ymm12 # shuffle xDxC -> DC00
116 _XFER_SIZE = 2*64*4 # 2 blocks, 64 rounds, 4 bytes/round
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/openbmc/linux/drivers/media/pci/cx25821/
H A Dcx25821-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include "cx25821-sram.h"
16 #include "cx25821-video.h"
19 MODULE_AUTHOR("Shu Lin - Hiep Huynh");
26 static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
320 [RISC_WRITECR >> 28] = 4, in cx25821_risc_decode()
332 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) { in cx25821_risc_decode()
356 /* PLL-A setting for the Audio Master Clock */ in cx25821_registers_init()
366 /* PLL-B setting for Mobilygen Host Bus Interface */ in cx25821_registers_init()
376 /* PLL-C setting for video upstream channel */ in cx25821_registers_init()
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/openbmc/u-boot/drivers/video/
H A Dipu_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Porting to u-boot:
10 * (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
58 #define DC_EVT_EOL 4
68 #define DC_EVT_NEW_DATA_W_0 4
133 DI_PIN15 = 4,
143 DI_SYNC_NONE = -1,
166 u32 disp_alt[4];
173 u32 reserved1[4];
201 u32 gamma_s_async[4];
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/openbmc/linux/drivers/clk/uniphier/
H A Dclk-uniphier-peri.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include "clk-uniphier.h"
9 #define UNIPHIER_PERI_CLK_UART(idx, ch) \ argument
10 UNIPHIER_CLK_GATE("uart" #ch, (idx), "uart", 0x24, 19 + (ch))
13 UNIPHIER_CLK_GATE("i2c-common", -1, "i2c", 0x20, 1)
15 #define UNIPHIER_PERI_CLK_I2C(idx, ch) \ argument
16 UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c-common", 0x24, 5 + (ch))
18 #define UNIPHIER_PERI_CLK_FI2C(idx, ch) \ argument
19 UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c", 0x24, 24 + (ch))
21 #define UNIPHIER_PERI_CLK_SCSSI(idx, ch) \ argument
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/openbmc/linux/drivers/scsi/
H A Dch.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * (c) 1996-2003 Gerd Knorr <kraxel@bytesex.org>
71 static int dt_id[CH_DT_MAX] = { [ 0 ... (CH_DT_MAX-1) ] = -1 };
76 /* tell the driver about vendor-specific slots */
77 static int vendor_firsts[CH_TYPES-4];
78 static int vendor_counts[CH_TYPES-4];
82 static const char * vendor_labels[CH_TYPES-4] = {
87 #define ch_printk(prefix, ch, fmt, a...) \ argument
88 sdev_prefix_printk(prefix, (ch)->device, (ch)->name, fmt, ##a)
93 ch_printk(KERN_DEBUG, ch, fmt, ##arg); \
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