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/openbmc/u-boot/arch/x86/dts/
H A Dedison.dts31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0>;
37 intel,apic-id = <0>;
53 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
54 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
55 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
60 reg = <0xff010080 0x100>;
61 reg-shift = <0>;
68 reg = <0xff010100 0x100>;
[all …]
/openbmc/u-boot/doc/driver-model/
H A Dof-plat.txt94 fifo-depth = <0x100>;
96 reg = <0xff0c0000 0x4000>;
104 pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
133 .fifo_depth = 0x100,
135 .interrupts = {0x0, 0x20, 0x4},
136 .clock_freq_min_max = {0x61a80, 0x8f0d180},
137 .vmmc_supply = 0xb,
138 .num_slots = 0x1,
145 .bus_width = 0x4,
147 .reg = {0xff0c0000, 0x4000},
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Drockchip-dw-mshc.yaml80 minimum: 0
82 default: 0
86 If not specified 0 deg will be used.
90 minimum: 0
114 reg = <0xff0c0000 0x4000>;
121 fifo-depth = <0x100>;
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml126 const: 0
135 "^ethernet-phy@[0-9a-f]$":
177 reg = <0xfffc4000 0x4000>;
179 cdns,rx-watermark = <0x44>;
181 local-mac-address = [3a 0e 03 04 05 06];
185 #size-cells = <0>;
188 reg = <0x1>;
205 interrupts = <0 59 4>, <0 59 4>;
206 reg = <0x0 0xff0c0000 0x0 0x1000>;
212 #size-cells = <0>;
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-tangier/acpi/
H A Dsouthcluster.asl13 Name (_ADR, 0)
14 Name (_BBN, 0)
20 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
22 /* IO Region 0 */
24 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
27 IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
31 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
36 0x00000000, 0x000ddcc0, 0x000ddccf, 0x00000000,
37 0x00000010, , , GP00)
39 /* PSH Memory Region 0 */
[all …]
/openbmc/qemu/hw/arm/
H A Dxlnx-zynqmp.c39 #define GEM_REVISION 0x40070106
41 #define GIC_BASE_ADDR 0xf9000000
42 #define GIC_DIST_ADDR 0xf9010000
43 #define GIC_CPU_ADDR 0xf9020000
44 #define GIC_VIFACE_ADDR 0xf9040000
45 #define GIC_VCPU_ADDR 0xf9060000
48 #define SATA_ADDR 0xFD0C0000
51 #define QSPI_ADDR 0xff0f0000
52 #define LQSPI_ADDR 0xc0000000
54 #define QSPI_DMA_ADDR 0xff0f0800
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp.dtsi22 #size-cells = <0>;
24 cpu0: cpu@0 {
29 reg = <0x0>;
37 reg = <0x1>;
46 reg = <0x2>;
55 reg = <0x3>;
63 CPU_SLEEP_0: cpu-sleep-0 {
65 arm,psci-suspend-param = <0x40000000>;
108 interrupts = <0 143 4>,
109 <0 144 4>,
[all …]
H A Drk3368.dtsi76 #address-cells = <0x2>;
77 #size-cells = <0x0>;
114 cpu_sleep: cpu-sleep-0 {
116 arm,psci-suspend-param = <0x1010000>;
117 entry-latency-us = <0x3fffffff>;
118 exit-latency-us = <0x40000000>;
119 min-residency-us = <0xffffffff>;
123 cpu_l0: cpu@0 {
126 reg = <0x0 0x0>;
136 reg = <0x0 0x1>;
[all …]
H A Drk3288.dtsi53 #size-cells = <0>;
60 reg = <0x500>;
85 reg = <0x501>;
91 reg = <0x502>;
97 reg = <0x503>;
111 reg = <0xff250000 0x4000>;
122 reg = <0xff600000 0x4000>;
123 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
134 reg = <0xffb20000 0x4000>;
135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
36 reg = <0x0>;
45 reg = <0x1>;
55 reg = <0x2>;
65 reg = <0x3>;
80 CPU_SLEEP_0: cpu-sleep-0 {
82 arm,psci-suspend-param = <0x40000000>;
123 reg = <0x0 0x3ed00000 0x0 0x40000>;
128 reg = <0x0 0x3ef00000 0x0 0x40000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3368.dtsi40 #address-cells = <0x2>;
41 #size-cells = <0x0>;
75 cpu_l0: cpu@0 {
78 reg = <0x0 0x0>;
86 reg = <0x0 0x1>;
94 reg = <0x0 0x2>;
102 reg = <0x0 0x3>;
110 reg = <0x0 0x100>;
118 reg = <0x0 0x101>;
126 reg = <0x0 0x102>;
[all …]
H A Drk3308.dtsi39 #size-cells = <0>;
41 cpu0: cpu@0 {
44 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
67 reg = <0x0 0x2>;
77 reg = <0x0 0x3>;
90 arm,psci-suspend-param = <0x0010000>;
104 cpu0_opp_table: opp-table-0 {
144 #clock-cells = <0>;
162 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3288.dtsi53 #size-cells = <0>;
60 reg = <0x500>;
71 reg = <0x501>;
82 reg = <0x502>;
93 reg = <0x503>;
103 cpu_opp_table: opp-table-0 {
163 * The rk3288 cannot use the memory area above 0xfe000000
173 reg = <0x0 0xfe000000 0x0 0x1000000>;
181 #clock-cells = <0>;
197 reg = <0x0 0xff810000 0x0 0x20>;
[all …]