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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dbrcm,bcm63xx-spi.yaml64 reg = <0x10000800 0x70c>;
70 #size-cells = <0>;
/openbmc/u-boot/arch/mips/mach-mt7620/
H A Dlowlevel_init.S27 #define DDR_CFG1_CHIP_WIDTH_MASK (0x3 << 16)
28 #define DDR_CFG1_BUS_WIDTH_MASK (0x3 << 12)
31 #define DDR_CFG1_SIZE_VAL 0x222e2323
35 #define DDR_CFG1_SIZE_VAL 0x22322323
39 #define DDR_CFG1_SIZE_VAL 0x22362323
43 #define DDR_CFG1_SIZE_VAL 0x223a2323
48 #define DDR_CFG1_CHIP_WIDTH_VAL (0x1 << 16)
51 #define DDR_CFG1_CHIP_WIDTH_VAL (0x2 << 16)
55 #define DDR_CFG1_BUS_WIDTH_VAL (0x2 << 12)
58 #define DDR_CFG1_BUS_WIDTH_VAL (0x3 << 12)
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dsama5d2_smc.h13 #define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x700)
14 #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x704)
15 #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x708)
16 #define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x70c)
17 #define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x710)
20 u32 setup; /* 0x600 SMC Setup Register */
21 u32 pulse; /* 0x604 SMC Pulse Register */
22 u32 cycle; /* 0x608 SMC Cycle Register */
23 u32 timings; /* 0x60C SMC Cycle Register */
24 u32 mode; /* 0x610 SMC Mode Register */
[all …]
/openbmc/linux/arch/mips/pci/
H A Dpci-mt7620.c24 #define RALINK_PCI_IO_MAP_BASE 0x10160000
25 #define RALINK_PCI_MEMORY_BASE 0x0
29 #define RALINK_CLKCFG1 0x30
30 #define RALINK_GPIOMODE 0x60
32 #define PPLL_CFG1 0x9c
35 #define PPLL_DRV 0xa0
43 #define RALINK_PCI_PCICFG_ADDR 0x00
46 #define RALINK_PCI_PCIENA 0x0C
49 #define RALINK_PCI_CONFIG_ADDR 0x20
50 #define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24
[all …]
/openbmc/linux/drivers/media/common/b2c2/
H A Dflexcop-reg.h11 FLEXCOP_UNK = 0,
18 FC_UNK = 0,
32 FC_USB = 0,
47 #define fc_data_Tag_ID_DVB 0x3e
48 #define fc_data_Tag_ID_ATSC 0x3f
49 #define fc_data_Tag_ID_IDSB 0x8b
51 #define fc_key_code_default 0x1
52 #define fc_key_code_even 0x2
53 #define fc_key_code_odd 0x3
64 FC_WRITE = 0,
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dgrf_rk3328.h31 u32 reserved1[(0x100 - 0x54) / 4];
49 u32 reserved2[(0x200 - 0x140) / 4];
66 u32 reserved3[(0x300 - 0x240) / 4];
75 u32 reserved4[(0x380 - 0x320) / 4];
84 u32 reserved5[(0x400 - 0x3a0) / 4];
86 u32 reserved6[(0x480 - 0x42c) / 4];
88 u32 reserved7[(0x4c0 - 0x494) / 4];
90 u32 reserved8[(0x500 - 0x4c8) / 4];
92 u32 reserved9[(0x520 - 0x508) / 4];
94 u32 reserved10[(0x5c8 - 0x528) / 4];
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dbrcm,bcm3380.dtsi19 reg = <0x14e00000 0x4>;
21 #size-cells = <0>;
24 cpu@0 {
27 reg = <0>;
47 #clock-cells = <0>;
54 reg = <0x14e00004 0x4>;
60 reg = <0x14e00008 0x4>;
73 reg = <0x12000000 0x1000>;
79 reg = <0x14e0008c 0x4>;
85 reg = <0x14e00090 0x4>;
[all …]
H A Dbrcm,bcm6368.dtsi20 reg = <0x10000000 0x4>;
22 #size-cells = <0>;
25 cpu@0 {
28 reg = <0>;
48 #clock-cells = <0>;
55 reg = <0x10000004 0x4>;
62 reg = <0x18000000 0x2000000>;
78 reg = <0x10000008 0x4>;
84 offset = <0x0>;
85 mask = <0x1>;
[all …]
H A Dbrcm,bcm6362.dtsi22 reg = <0x10000000 0x4>;
24 #size-cells = <0>;
27 cpu@0 {
30 reg = <0>;
50 #clock-cells = <0>;
56 #clock-cells = <0>;
63 reg = <0x10000004 0x4>;
76 reg = <0x10000008 0x4>;
82 offset = <0x0>;
83 mask = <0x1>;
[all …]
H A Dbrcm,bcm6358.dtsi20 reg = <0xfffe0000 0x4>;
22 #size-cells = <0>;
25 cpu@0 {
28 reg = <0>;
48 #clock-cells = <0>;
55 reg = <0xfffe0004 0x4>;
62 reg = <0x1e000000 0x2000000>;
78 reg = <0xfffe0008 0x4>;
84 offset = <0x0>;
85 mask = <0x1>;
[all …]
H A Dbrcm,bcm63268.dtsi22 reg = <0x10000000 0x4>;
24 #size-cells = <0>;
27 cpu@0 {
30 reg = <0>;
50 #clock-cells = <0>;
56 #clock-cells = <0>;
63 reg = <0x10000004 0x4>;
69 reg = <0x100000ac 0x4>;
82 reg = <0x10000008 0x4>;
88 offset = <0x0>;
[all …]
/openbmc/linux/arch/mips/boot/dts/brcm/
H A Dbcm6358.dtsi13 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
33 #clock-cells = <0>;
47 #address-cells = <0>;
63 reg = <0xfffe0004 0x4>;
69 reg = <0xfffe0008 0x4>;
74 offset = <0x0>;
75 mask = <0x1>;
81 reg = <0xfffe000c 0x8>,
[all …]
H A Dbcm6362.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
42 #clock-cells = <0>;
58 #address-cells = <0>;
74 reg = <0x10000004 0x4>;
80 reg = <0x10000008 0x4>;
85 offset = <0x0>;
86 mask = <0x1>;
[all …]
H A Dbcm6368.dtsi13 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
33 #clock-cells = <0>;
48 #address-cells = <0>;
64 reg = <0x10000004 0x4>;
70 reg = <0x10000008 0x4>;
75 offset = <0x0>;
76 mask = <0x1>;
82 reg = <0x10000010 0x4>;
[all …]
H A Dbcm63268.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
42 #clock-cells = <0>;
58 #address-cells = <0>;
74 reg = <0x10000004 0x4>;
80 reg = <0x10000008 0x4>;
85 offset = <0x0>;
86 mask = <0x1>;
[all …]
/openbmc/qemu/tests/qtest/
H A Dnpcm_gmac-test.c27 #define PCS_BASE_ADDRESS 0xf0780000
28 #define NPCM_PCS_IND_AC_BA 0x1fe
43 .base_addr = 0xf0802000
47 .base_addr = 0xf0804000
56 g_assert_true(diff >= 0 && diff < ARRAY_SIZE(gmac_module_list)); in gmac_module_index()
64 NPCM_DMA_BUS_MODE = 0x1000,
65 NPCM_DMA_XMT_POLL_DEMAND = 0x1004,
66 NPCM_DMA_RCV_POLL_DEMAND = 0x1008,
67 NPCM_DMA_RCV_BASE_ADDR = 0x100c,
68 NPCM_DMA_TX_BASE_ADDR = 0x1010,
[all …]
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhikey970-pinctrl.dtsi16 reg = <0x0 0xe896c000 0x0 0x72c>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
22 pinctrl-single,gpio-range = <&range 0 82 0>;
26 0x054 MUX_M2 /* UART0_RXD */
27 0x058 MUX_M2 /* UART0_TXD */
33 0x700 MUX_M2 /* UART2_CTS_N */
34 0x704 MUX_M2 /* UART2_RTS_N */
35 0x708 MUX_M2 /* UART2_RXD */
[all …]
/openbmc/linux/drivers/accel/habanalabs/goya/
H A Dgoya_coresight.c18 #define SPMU_EVENT_TYPES_OFFSET 0x400
220 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", in goya_coresight_timeout()
225 return 0; in goya_coresight_timeout()
243 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in goya_config_stm()
251 WREG32(base_reg + 0xE80, 0x80004); in goya_config_stm()
252 WREG32(base_reg + 0xD64, 7); in goya_config_stm()
253 WREG32(base_reg + 0xD60, 0); in goya_config_stm()
254 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in goya_config_stm()
255 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask)); in goya_config_stm()
256 WREG32(base_reg + 0xD60, 1); in goya_config_stm()
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
/openbmc/linux/drivers/phy/samsung/
H A Dphy-exynos4x12-usb2.c18 #define EXYNOS_4x12_UPHYPWR 0x0
20 #define EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND BIT(0)
55 #define EXYNOS_4x12_UPHYCLK 0x4
57 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK (0x7 << 0)
58 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET 0
59 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6 (0x0 << 0)
60 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ (0x1 << 0)
61 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
62 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2 (0x3 << 0)
63 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ (0x4 << 0)
[all …]
H A Dphy-exynos5250-usb2.c16 #define EXYNOS_5250_REFCLKSEL_CRYSTAL 0x0
17 #define EXYNOS_5250_REFCLKSEL_XO 0x1
18 #define EXYNOS_5250_REFCLKSEL_CLKCORE 0x2
20 #define EXYNOS_5250_FSEL_9MHZ6 0x0
21 #define EXYNOS_5250_FSEL_10MHZ 0x1
22 #define EXYNOS_5250_FSEL_12MHZ 0x2
23 #define EXYNOS_5250_FSEL_19MHZ2 0x3
24 #define EXYNOS_5250_FSEL_20MHZ 0x4
25 #define EXYNOS_5250_FSEL_24MHZ 0x5
26 #define EXYNOS_5250_FSEL_50MHZ 0x7
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Drv6xxd.h27 #define SPLL_CNTL_MODE 0x60c
30 #define GENERAL_PWRMGT 0x618
31 # define GLOBAL_PWRMGT_EN (1 << 0)
47 #define MCLK_PWRMGT_CNTL 0x624
48 # define MPLL_PWRMGT_OFF (1 << 0)
78 #define MPLL_FREQ_LEVEL_0 0x6e8
79 # define LEVEL0_MPLL_POST_DIV(x) ((x) << 0)
80 # define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0)
82 # define LEVEL0_MPLL_FB_DIV_MASK (0xfff << 8)
84 # define LEVEL0_MPLL_REF_DIV_MASK (0x3f << 20)
[all …]
/openbmc/linux/drivers/usb/dwc3/
H A Ddwc3-am62.c23 #define USBSS_PID 0x0
24 #define USBSS_OVERCURRENT_CTRL 0x4
25 #define USBSS_PHY_CONFIG 0x8
26 #define USBSS_PHY_TEST 0xc
27 #define USBSS_CORE_STAT 0x14
28 #define USBSS_HOST_VBUS_CTRL 0x18
29 #define USBSS_MODE_CONTROL 0x1c
30 #define USBSS_WAKEUP_CONFIG 0x30
31 #define USBSS_WAKEUP_STAT 0x34
32 #define USBSS_OVERRIDE_CONFIG 0x38
[all …]
/openbmc/linux/drivers/gpu/drm/tegra/
H A Ddc.h176 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000
177 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
179 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
180 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
181 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008
182 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
183 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
184 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010
185 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
186 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dpci.c27 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
28 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
29 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
34 0x0029,
36 0x2096),
40 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
44 0x002A,
46 0x1C71),
49 0x002A,
51 0xE01F),
[all …]

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