27 #define PCS_BASE_ADDRESS 0xf0780000
28 #define NPCM_PCS_IND_AC_BA 0x1fe
43         .base_addr  = 0xf0802000
47         .base_addr  = 0xf0804000
56     g_assert_true(diff >= 0 && diff < ARRAY_SIZE(gmac_module_list));  in gmac_module_index()
64     NPCM_DMA_BUS_MODE = 0x1000,
65     NPCM_DMA_XMT_POLL_DEMAND = 0x1004,
66     NPCM_DMA_RCV_POLL_DEMAND = 0x1008,
67     NPCM_DMA_RCV_BASE_ADDR = 0x100c,
68     NPCM_DMA_TX_BASE_ADDR = 0x1010,
69     NPCM_DMA_STATUS = 0x1014,
70     NPCM_DMA_CONTROL = 0x1018,
71     NPCM_DMA_INTR_ENA = 0x101c,
72     NPCM_DMA_MISSED_FRAME_CTR = 0x1020,
73     NPCM_DMA_HOST_TX_DESC = 0x1048,
74     NPCM_DMA_HOST_RX_DESC = 0x104c,
75     NPCM_DMA_CUR_TX_BUF_ADDR = 0x1050,
76     NPCM_DMA_CUR_RX_BUF_ADDR = 0x1054,
77     NPCM_DMA_HW_FEATURE = 0x1058,
80     NPCM_GMAC_MAC_CONFIG = 0x0,
81     NPCM_GMAC_FRAME_FILTER = 0x4,
82     NPCM_GMAC_HASH_HIGH = 0x8,
83     NPCM_GMAC_HASH_LOW = 0xc,
84     NPCM_GMAC_MII_ADDR = 0x10,
85     NPCM_GMAC_MII_DATA = 0x14,
86     NPCM_GMAC_FLOW_CTRL = 0x18,
87     NPCM_GMAC_VLAN_FLAG = 0x1c,
88     NPCM_GMAC_VERSION = 0x20,
89     NPCM_GMAC_WAKEUP_FILTER = 0x28,
90     NPCM_GMAC_PMT = 0x2c,
91     NPCM_GMAC_LPI_CTRL = 0x30,
92     NPCM_GMAC_TIMER_CTRL = 0x34,
93     NPCM_GMAC_INT_STATUS = 0x38,
94     NPCM_GMAC_INT_MASK = 0x3c,
95     NPCM_GMAC_MAC0_ADDR_HI = 0x40,
96     NPCM_GMAC_MAC0_ADDR_LO = 0x44,
97     NPCM_GMAC_MAC1_ADDR_HI = 0x48,
98     NPCM_GMAC_MAC1_ADDR_LO = 0x4c,
99     NPCM_GMAC_MAC2_ADDR_HI = 0x50,
100     NPCM_GMAC_MAC2_ADDR_LO = 0x54,
101     NPCM_GMAC_MAC3_ADDR_HI = 0x58,
102     NPCM_GMAC_MAC3_ADDR_LO = 0x5c,
103     NPCM_GMAC_RGMII_STATUS = 0xd8,
104     NPCM_GMAC_WATCHDOG = 0xdc,
105     NPCM_GMAC_PTP_TCR = 0x700,
106     NPCM_GMAC_PTP_SSIR = 0x704,
107     NPCM_GMAC_PTP_STSR = 0x708,
108     NPCM_GMAC_PTP_STNSR = 0x70c,
109     NPCM_GMAC_PTP_STSUR = 0x710,
110     NPCM_GMAC_PTP_STNSUR = 0x714,
111     NPCM_GMAC_PTP_TAR = 0x718,
112     NPCM_GMAC_PTP_TTSR = 0x71c,
115     NPCM_PCS_SR_CTL_ID1 = 0x3c0008,
116     NPCM_PCS_SR_CTL_ID2 = 0x3c000a,
117     NPCM_PCS_SR_CTL_STS = 0x3c0010,
119     NPCM_PCS_SR_MII_CTRL = 0x3e0000,
120     NPCM_PCS_SR_MII_STS = 0x3e0002,
121     NPCM_PCS_SR_MII_DEV_ID1 = 0x3e0004,
122     NPCM_PCS_SR_MII_DEV_ID2 = 0x3e0006,
123     NPCM_PCS_SR_MII_AN_ADV = 0x3e0008,
124     NPCM_PCS_SR_MII_LP_BABL = 0x3e000a,
125     NPCM_PCS_SR_MII_AN_EXPN = 0x3e000c,
126     NPCM_PCS_SR_MII_EXT_STS = 0x3e001e,
128     NPCM_PCS_SR_TIM_SYNC_ABL = 0x3e0e10,
129     NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR = 0x3e0e12,
130     NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR = 0x3e0e14,
131     NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR = 0x3e0e16,
132     NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR = 0x3e0e18,
133     NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR = 0x3e0e1a,
134     NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR = 0x3e0e1c,
135     NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR = 0x3e0e1e,
136     NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR = 0x3e0e20,
138     NPCM_PCS_VR_MII_MMD_DIG_CTRL1 = 0x3f0000,
139     NPCM_PCS_VR_MII_AN_CTRL = 0x3f0002,
140     NPCM_PCS_VR_MII_AN_INTR_STS = 0x3f0004,
141     NPCM_PCS_VR_MII_TC = 0x3f0006,
142     NPCM_PCS_VR_MII_DBG_CTRL = 0x3f000a,
143     NPCM_PCS_VR_MII_EEE_MCTRL0 = 0x3f000c,
144     NPCM_PCS_VR_MII_EEE_TXTIMER = 0x3f0010,
145     NPCM_PCS_VR_MII_EEE_RXTIMER = 0x3f0012,
146     NPCM_PCS_VR_MII_LINK_TIMER_CTRL = 0x3f0014,
147     NPCM_PCS_VR_MII_EEE_MCTRL1 = 0x3f0016,
148     NPCM_PCS_VR_MII_DIG_STS = 0x3f0020,
149     NPCM_PCS_VR_MII_ICG_ERRCNT1 = 0x3f0022,
150     NPCM_PCS_VR_MII_MISC_STS = 0x3f0030,
151     NPCM_PCS_VR_MII_RX_LSTS = 0x3f0040,
152     NPCM_PCS_VR_MII_MP_TX_BSTCTRL0 = 0x3f0070,
153     NPCM_PCS_VR_MII_MP_TX_LVLCTRL0 = 0x3f0074,
154     NPCM_PCS_VR_MII_MP_TX_GENCTRL0 = 0x3f007a,
155     NPCM_PCS_VR_MII_MP_TX_GENCTRL1 = 0x3f007c,
156     NPCM_PCS_VR_MII_MP_TX_STS = 0x3f0090,
157     NPCM_PCS_VR_MII_MP_RX_GENCTRL0 = 0x3f00b0,
158     NPCM_PCS_VR_MII_MP_RX_GENCTRL1 = 0x3f00b2,
159     NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0 = 0x3f00ba,
160     NPCM_PCS_VR_MII_MP_MPLL_CTRL0 = 0x3f00f0,
161     NPCM_PCS_VR_MII_MP_MPLL_CTRL1 = 0x3f00f2,
162     NPCM_PCS_VR_MII_MP_MPLL_STS = 0x3f0110,
163     NPCM_PCS_VR_MII_MP_MISC_CTRL2 = 0x3f0126,
164     NPCM_PCS_VR_MII_MP_LVL_CTRL = 0x3f0130,
165     NPCM_PCS_VR_MII_MP_MISC_CTRL0 = 0x3f0132,
166     NPCM_PCS_VR_MII_MP_MISC_CTRL1 = 0x3f0134,
167     NPCM_PCS_VR_MII_DIG_CTRL2 = 0x3f01c2,
168     NPCM_PCS_VR_MII_DIG_ERRCNT_SEL = 0x3f01c4,
187     } while (0)  in test_init()
189     CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100);  in test_init()
190     CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0);  in test_init()
191     CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0);  in test_init()
192     CHECK_REG32(NPCM_DMA_RCV_BASE_ADDR, 0);  in test_init()
193     CHECK_REG32(NPCM_DMA_TX_BASE_ADDR, 0);  in test_init()
194     CHECK_REG32(NPCM_DMA_STATUS, 0);  in test_init()
195     CHECK_REG32(NPCM_DMA_CONTROL, 0);  in test_init()
196     CHECK_REG32(NPCM_DMA_INTR_ENA, 0);  in test_init()
197     CHECK_REG32(NPCM_DMA_MISSED_FRAME_CTR, 0);  in test_init()
198     CHECK_REG32(NPCM_DMA_HOST_TX_DESC, 0);  in test_init()
199     CHECK_REG32(NPCM_DMA_HOST_RX_DESC, 0);  in test_init()
200     CHECK_REG32(NPCM_DMA_CUR_TX_BUF_ADDR, 0);  in test_init()
201     CHECK_REG32(NPCM_DMA_CUR_RX_BUF_ADDR, 0);  in test_init()
202     CHECK_REG32(NPCM_DMA_HW_FEATURE, 0x100d4f37);  in test_init()
204     CHECK_REG32(NPCM_GMAC_MAC_CONFIG, 0);  in test_init()
205     CHECK_REG32(NPCM_GMAC_FRAME_FILTER, 0);  in test_init()
206     CHECK_REG32(NPCM_GMAC_HASH_HIGH, 0);  in test_init()
207     CHECK_REG32(NPCM_GMAC_HASH_LOW, 0);  in test_init()
208     CHECK_REG32(NPCM_GMAC_MII_ADDR, 0);  in test_init()
209     CHECK_REG32(NPCM_GMAC_MII_DATA, 0);  in test_init()
210     CHECK_REG32(NPCM_GMAC_FLOW_CTRL, 0);  in test_init()
211     CHECK_REG32(NPCM_GMAC_VLAN_FLAG, 0);  in test_init()
212     CHECK_REG32(NPCM_GMAC_VERSION, 0x00001032);  in test_init()
213     CHECK_REG32(NPCM_GMAC_WAKEUP_FILTER, 0);  in test_init()
214     CHECK_REG32(NPCM_GMAC_PMT, 0);  in test_init()
215     CHECK_REG32(NPCM_GMAC_LPI_CTRL, 0);  in test_init()
216     CHECK_REG32(NPCM_GMAC_TIMER_CTRL, 0x03e80000);  in test_init()
217     CHECK_REG32(NPCM_GMAC_INT_STATUS, 0);  in test_init()
218     CHECK_REG32(NPCM_GMAC_INT_MASK, 0);  in test_init()
219     CHECK_REG32(NPCM_GMAC_MAC0_ADDR_HI, 0x8000ffff);  in test_init()
220     CHECK_REG32(NPCM_GMAC_MAC0_ADDR_LO, 0xffffffff);  in test_init()
221     CHECK_REG32(NPCM_GMAC_MAC1_ADDR_HI, 0x0000ffff);  in test_init()
222     CHECK_REG32(NPCM_GMAC_MAC1_ADDR_LO, 0xffffffff);  in test_init()
223     CHECK_REG32(NPCM_GMAC_MAC2_ADDR_HI, 0x0000ffff);  in test_init()
224     CHECK_REG32(NPCM_GMAC_MAC2_ADDR_LO, 0xffffffff);  in test_init()
225     CHECK_REG32(NPCM_GMAC_MAC3_ADDR_HI, 0x0000ffff);  in test_init()
226     CHECK_REG32(NPCM_GMAC_MAC3_ADDR_LO, 0xffffffff);  in test_init()
227     CHECK_REG32(NPCM_GMAC_RGMII_STATUS, 0);  in test_init()
228     CHECK_REG32(NPCM_GMAC_WATCHDOG, 0);  in test_init()
229     CHECK_REG32(NPCM_GMAC_PTP_TCR, 0x00002000);  in test_init()
230     CHECK_REG32(NPCM_GMAC_PTP_SSIR, 0);  in test_init()
231     CHECK_REG32(NPCM_GMAC_PTP_STSR, 0);  in test_init()
232     CHECK_REG32(NPCM_GMAC_PTP_STNSR, 0);  in test_init()
233     CHECK_REG32(NPCM_GMAC_PTP_STSUR, 0);  in test_init()
234     CHECK_REG32(NPCM_GMAC_PTP_STNSUR, 0);  in test_init()
235     CHECK_REG32(NPCM_GMAC_PTP_TAR, 0);  in test_init()
236     CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0);  in test_init()
255     for (int i = 0; i < ARRAY_SIZE(gmac_module_list); ++i) {  in main()