Lines Matching +full:0 +full:x70c
23 #define USBSS_PID 0x0
24 #define USBSS_OVERCURRENT_CTRL 0x4
25 #define USBSS_PHY_CONFIG 0x8
26 #define USBSS_PHY_TEST 0xc
27 #define USBSS_CORE_STAT 0x14
28 #define USBSS_HOST_VBUS_CTRL 0x18
29 #define USBSS_MODE_CONTROL 0x1c
30 #define USBSS_WAKEUP_CONFIG 0x30
31 #define USBSS_WAKEUP_STAT 0x34
32 #define USBSS_OVERRIDE_CONFIG 0x38
33 #define USBSS_IRQ_MISC_STATUS_RAW 0x430
34 #define USBSS_IRQ_MISC_STATUS 0x434
35 #define USBSS_IRQ_MISC_ENABLE_SET 0x438
36 #define USBSS_IRQ_MISC_ENABLE_CLR 0x43c
37 #define USBSS_IRQ_MISC_EOI 0x440
38 #define USBSS_INTR_TEST 0x490
39 #define USBSS_VBUS_FILTER 0x614
40 #define USBSS_VBUS_STAT 0x618
41 #define USBSS_DEBUG_CFG 0x708
42 #define USBSS_DEBUG_DATA 0x70c
43 #define USBSS_HOST_HUB_CTRL 0x714
48 #define USBSS_PHY_LANE_REVERSE BIT(0)
55 #define USBSS_MODE_VALID BIT(0)
61 #define USBSS_WAKEUP_CFG_VBUSVALID_EN BIT(0)
68 #define USBSS_WAKEUP_CFG_NONE 0
75 #define USBSS_WAKEUP_STAT_CLR BIT(0)
94 #define USBSS_IRQ_MISC_EOI_VECTOR BIT(0)
98 #define USBSS_VBUS_STAT_VBUSVALID BIT(0)
101 #define PHY_PLL_REFCLK_MASK GENMASK(3, 0)
159 0, &args); in phy_syscon_pll_refclk()
164 am62->offset = args.args[0]; in phy_syscon_pll_refclk()
172 return 0; in phy_syscon_pll_refclk()
191 am62->usbss = devm_platform_ioremap_resource(pdev, 0); in dwc3_ti_probe()
206 for (i = 0; i < ARRAY_SIZE(dwc3_ti_rate_table); i++) { in dwc3_ti_probe()
262 return 0; in dwc3_ti_probe()
320 return 0; in dwc3_ti_suspend_common()
338 return 0; in dwc3_ti_resume_common()