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/openbmc/linux/Documentation/devicetree/bindings/peci/
H A Dpeci-controller.yaml30 reg = <0x1e78b000 0x100>;
H A Dpeci-aspeed.yaml65 reg = <0x1e78b000 0x100>;
/openbmc/u-boot/cmd/aspeed/
H A Dpeci.c6 #define AST_SCU (0x1e6e2000)
8 #define AST_SCU_SYSRST_CTRL (AST_SCU + 0x04)
10 #define AST_SCU_SYSRST_CLR2 (AST_SCU + 0x54)
13 #define AST_PECI (0x1e78b000)
14 #define AST_PECI_CTRL (AST_PECI + 0x00)
15 #define AST_PECI_TIMING (AST_PECI + 0x04)
16 #define AST_PECI_CMD (AST_PECI + 0x08)
17 #define AST_PECI_RW_LEN (AST_PECI + 0x0C)
18 #define AST_PECI_EXP_FCS (AST_PECI + 0x10)
19 #define AST_PECI_CAP_FCS (AST_PECI + 0x14)
[all …]
/openbmc/qemu/hw/arm/
H A Daspeed_ast2400.c26 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
29 [ASPEED_DEV_SPI_BOOT] = 0x00000000,
30 [ASPEED_DEV_IOMEM] = 0x1E600000,
31 [ASPEED_DEV_FMC] = 0x1E620000,
32 [ASPEED_DEV_SPI1] = 0x1E630000,
33 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
34 [ASPEED_DEV_UHCI] = 0x1E6B0000,
35 [ASPEED_DEV_VIC] = 0x1E6C0000,
36 [ASPEED_DEV_SDMC] = 0x1E6E0000,
37 [ASPEED_DEV_SCU] = 0x1E6E2000,
[all …]
H A Daspeed_ast2600.c21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000
25 [ASPEED_DEV_SPI_BOOT] = 0x00000000,
26 [ASPEED_DEV_SRAM] = 0x10000000,
27 [ASPEED_DEV_DPMCU] = 0x18000000,
28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
29 [ASPEED_DEV_IOMEM] = 0x1E600000,
30 [ASPEED_DEV_PWM] = 0x1E610000,
31 [ASPEED_DEV_FMC] = 0x1E620000,
32 [ASPEED_DEV_SPI1] = 0x1E630000,
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-g4.dtsi36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
47 reg = <0x40000000 0>;
57 reg = <0x1e620000 0x94>, <0x20000000 0x10000000>;
59 #size-cells = <0>;
64 flash@0 {
65 reg = < 0 >;
102 reg = <0x1e630000 0x18>, <0x30000000 0x10000000>;
104 #size-cells = <0>;
[all …]
H A Daspeed-g6.dtsi48 #size-cells = <0>;
54 reg = <0xf00>;
60 reg = <0xf01>;
78 reg = <0x1e6e0000 0x174>;
79 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
95 reg = <0x40461000 0x1000>,
96 <0x40462000 0x1000>,
97 <0x40464000 0x2000>,
98 <0x40466000 0x2000>;
103 reg = <0x1e600000 0x100>;
[all …]
H A Daspeed-g5.dtsi37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x80000000 0>;
58 reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
60 #size-cells = <0>;
65 flash@0 {
66 reg = < 0 >;
89 reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
91 #size-cells = <0>;
[all …]