1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/clock/aspeed-clock.h> 3#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h> 4 5/ { 6 model = "Aspeed BMC"; 7 compatible = "aspeed,ast2500"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 interrupt-parent = <&vic>; 11 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c6 = &i2c6; 20 i2c7 = &i2c7; 21 i2c8 = &i2c8; 22 i2c9 = &i2c9; 23 i2c10 = &i2c10; 24 i2c11 = &i2c11; 25 i2c12 = &i2c12; 26 i2c13 = &i2c13; 27 serial0 = &uart1; 28 serial1 = &uart2; 29 serial2 = &uart3; 30 serial3 = &uart4; 31 serial4 = &uart5; 32 serial5 = &vuart; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu@0 { 40 compatible = "arm,arm1176jzf-s"; 41 device_type = "cpu"; 42 reg = <0>; 43 }; 44 }; 45 46 memory@80000000 { 47 device_type = "memory"; 48 reg = <0x80000000 0>; 49 }; 50 51 ahb { 52 compatible = "simple-bus"; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 ranges; 56 57 fmc: spi@1e620000 { 58 reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>; 59 #address-cells = <1>; 60 #size-cells = <0>; 61 compatible = "aspeed,ast2500-fmc"; 62 clocks = <&syscon ASPEED_CLK_AHB>; 63 status = "disabled"; 64 interrupts = <19>; 65 flash@0 { 66 reg = < 0 >; 67 compatible = "jedec,spi-nor"; 68 spi-max-frequency = <50000000>; 69 spi-rx-bus-width = <2>; 70 status = "disabled"; 71 }; 72 flash@1 { 73 reg = < 1 >; 74 compatible = "jedec,spi-nor"; 75 spi-max-frequency = <50000000>; 76 spi-rx-bus-width = <2>; 77 status = "disabled"; 78 }; 79 flash@2 { 80 reg = < 2 >; 81 compatible = "jedec,spi-nor"; 82 spi-max-frequency = <50000000>; 83 spi-rx-bus-width = <2>; 84 status = "disabled"; 85 }; 86 }; 87 88 spi1: spi@1e630000 { 89 reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>; 90 #address-cells = <1>; 91 #size-cells = <0>; 92 compatible = "aspeed,ast2500-spi"; 93 clocks = <&syscon ASPEED_CLK_AHB>; 94 status = "disabled"; 95 flash@0 { 96 reg = < 0 >; 97 compatible = "jedec,spi-nor"; 98 spi-max-frequency = <50000000>; 99 spi-rx-bus-width = <2>; 100 status = "disabled"; 101 }; 102 flash@1 { 103 reg = < 1 >; 104 compatible = "jedec,spi-nor"; 105 spi-max-frequency = <50000000>; 106 spi-rx-bus-width = <2>; 107 status = "disabled"; 108 }; 109 }; 110 111 spi2: spi@1e631000 { 112 reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>; 113 #address-cells = <1>; 114 #size-cells = <0>; 115 compatible = "aspeed,ast2500-spi"; 116 clocks = <&syscon ASPEED_CLK_AHB>; 117 status = "disabled"; 118 flash@0 { 119 reg = < 0 >; 120 compatible = "jedec,spi-nor"; 121 spi-max-frequency = <50000000>; 122 spi-rx-bus-width = <2>; 123 status = "disabled"; 124 }; 125 flash@1 { 126 reg = < 1 >; 127 compatible = "jedec,spi-nor"; 128 spi-max-frequency = <50000000>; 129 spi-rx-bus-width = <2>; 130 status = "disabled"; 131 }; 132 }; 133 134 vic: interrupt-controller@1e6c0080 { 135 compatible = "aspeed,ast2400-vic"; 136 interrupt-controller; 137 #interrupt-cells = <1>; 138 valid-sources = <0xfefff7ff 0x0807ffff>; 139 reg = <0x1e6c0080 0x80>; 140 }; 141 142 cvic: interrupt-controller@1e6c2000 { 143 compatible = "aspeed,ast2500-cvic", "aspeed,cvic"; 144 valid-sources = <0xffffffff>; 145 copro-sw-interrupts = <1>; 146 reg = <0x1e6c2000 0x80>; 147 }; 148 149 mac0: ethernet@1e660000 { 150 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 151 reg = <0x1e660000 0x180>; 152 interrupts = <2>; 153 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; 154 status = "disabled"; 155 }; 156 157 mac1: ethernet@1e680000 { 158 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 159 reg = <0x1e680000 0x180>; 160 interrupts = <3>; 161 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; 162 status = "disabled"; 163 }; 164 165 ehci0: usb@1e6a1000 { 166 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 167 reg = <0x1e6a1000 0x100>; 168 interrupts = <5>; 169 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_usb2ah_default>; 172 status = "disabled"; 173 }; 174 175 ehci1: usb@1e6a3000 { 176 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 177 reg = <0x1e6a3000 0x100>; 178 interrupts = <13>; 179 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_usb2bh_default>; 182 status = "disabled"; 183 }; 184 185 uhci: usb@1e6b0000 { 186 compatible = "aspeed,ast2500-uhci", "generic-uhci"; 187 reg = <0x1e6b0000 0x100>; 188 interrupts = <14>; 189 #ports = <2>; 190 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; 191 status = "disabled"; 192 /* 193 * No default pinmux, it will follow EHCI, use an explicit pinmux 194 * override if you don't enable EHCI 195 */ 196 }; 197 198 vhub: usb-vhub@1e6a0000 { 199 compatible = "aspeed,ast2500-usb-vhub"; 200 reg = <0x1e6a0000 0x300>; 201 interrupts = <5>; 202 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 203 aspeed,vhub-downstream-ports = <5>; 204 aspeed,vhub-generic-endpoints = <15>; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_usb2ad_default>; 207 status = "disabled"; 208 }; 209 210 apb@1e6e0000 { 211 compatible = "simple-bus"; 212 reg = <0x1e6e0000 0x00010000>; 213 #address-cells = <1>; 214 #size-cells = <1>; 215 ranges; 216 217 edac: memory-controller@1e6e0000 { 218 compatible = "aspeed,ast2500-sdram-edac"; 219 reg = <0x1e6e0000 0x174>; 220 interrupts = <0>; 221 status = "disabled"; 222 }; 223 224 syscon: syscon@1e6e2000 { 225 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; 226 reg = <0x1e6e2000 0x1a8>; 227 #address-cells = <1>; 228 #size-cells = <1>; 229 ranges = <0 0x1e6e2000 0x1000>; 230 #clock-cells = <1>; 231 #reset-cells = <1>; 232 233 scu_ic: interrupt-controller@18 { 234 #interrupt-cells = <1>; 235 compatible = "aspeed,ast2500-scu-ic"; 236 reg = <0x18 0x4>; 237 interrupts = <21>; 238 interrupt-controller; 239 }; 240 241 p2a: p2a-control@2c { 242 compatible = "aspeed,ast2500-p2a-ctrl"; 243 reg = <0x2c 0x4>; 244 status = "disabled"; 245 }; 246 247 silicon-id@7c { 248 compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; 249 reg = <0x7c 0x4 0x150 0x8>; 250 }; 251 252 pinctrl: pinctrl@80 { 253 compatible = "aspeed,ast2500-pinctrl"; 254 reg = <0x80 0x18>, <0xa0 0x10>; 255 aspeed,external-nodes = <&gfx>, <&lhc>; 256 }; 257 }; 258 259 rng: hwrng@1e6e2078 { 260 compatible = "timeriomem_rng"; 261 reg = <0x1e6e2078 0x4>; 262 period = <1>; 263 quality = <100>; 264 }; 265 266 hace: crypto@1e6e3000 { 267 compatible = "aspeed,ast2500-hace"; 268 reg = <0x1e6e3000 0x100>; 269 interrupts = <4>; 270 clocks = <&syscon ASPEED_CLK_GATE_YCLK>; 271 resets = <&syscon ASPEED_RESET_HACE>; 272 }; 273 274 gfx: display@1e6e6000 { 275 compatible = "aspeed,ast2500-gfx", "syscon"; 276 reg = <0x1e6e6000 0x1000>; 277 reg-io-width = <4>; 278 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; 279 resets = <&syscon ASPEED_RESET_CRT1>; 280 syscon = <&syscon>; 281 status = "disabled"; 282 interrupts = <0x19>; 283 }; 284 285 xdma: xdma@1e6e7000 { 286 compatible = "aspeed,ast2500-xdma"; 287 reg = <0x1e6e7000 0x100>; 288 clocks = <&syscon ASPEED_CLK_GATE_BCLK>; 289 resets = <&syscon ASPEED_RESET_XDMA>; 290 interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>; 291 aspeed,pcie-device = "bmc"; 292 aspeed,scu = <&syscon>; 293 status = "disabled"; 294 }; 295 296 adc: adc@1e6e9000 { 297 compatible = "aspeed,ast2500-adc"; 298 reg = <0x1e6e9000 0xb0>; 299 clocks = <&syscon ASPEED_CLK_APB>; 300 resets = <&syscon ASPEED_RESET_ADC>; 301 #io-channel-cells = <1>; 302 status = "disabled"; 303 }; 304 }; 305 306 /* There's another APB mapping at 0x1e6f0000 for 0x00010000 */ 307 308 video: video@1e700000 { 309 compatible = "aspeed,ast2500-video-engine"; 310 reg = <0x1e700000 0x1000>; 311 clocks = <&syscon ASPEED_CLK_GATE_VCLK>, 312 <&syscon ASPEED_CLK_GATE_ECLK>; 313 clock-names = "vclk", "eclk"; 314 interrupts = <7>; 315 status = "disabled"; 316 }; 317 318 sram: sram@1e720000 { 319 compatible = "mmio-sram"; 320 reg = <0x1e720000 0x9000>; // 36K 321 ranges; 322 #address-cells = <1>; 323 #size-cells = <1>; 324 }; 325 326 sdmmc: sd-controller@1e740000 { 327 compatible = "aspeed,ast2500-sd-controller"; 328 reg = <0x1e740000 0x100>; 329 #address-cells = <1>; 330 #size-cells = <1>; 331 ranges = <0 0x1e740000 0x10000>; 332 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; 333 status = "disabled"; 334 335 sdhci0: sdhci@100 { 336 compatible = "aspeed,ast2500-sdhci"; 337 reg = <0x100 0x100>; 338 interrupts = <26>; 339 sdhci,auto-cmd12; 340 clocks = <&syscon ASPEED_CLK_SDIO>; 341 status = "disabled"; 342 }; 343 344 sdhci1: sdhci@200 { 345 compatible = "aspeed,ast2500-sdhci"; 346 reg = <0x200 0x100>; 347 interrupts = <26>; 348 sdhci,auto-cmd12; 349 clocks = <&syscon ASPEED_CLK_SDIO>; 350 status = "disabled"; 351 }; 352 }; 353 354 apb@1e780000 { 355 compatible = "simple-bus"; 356 reg = <0x1e780000 0x00010000>; 357 #address-cells = <1>; 358 #size-cells = <1>; 359 ranges; 360 361 gpio: gpio@1e780000 { 362 #gpio-cells = <2>; 363 gpio-controller; 364 compatible = "aspeed,ast2500-gpio"; 365 reg = <0x1e780000 0x200>; 366 interrupts = <20>; 367 gpio-ranges = <&pinctrl 0 0 232>; 368 clocks = <&syscon ASPEED_CLK_APB>; 369 interrupt-controller; 370 #interrupt-cells = <2>; 371 }; 372 373 sgpio: sgpio@1e780200 { 374 #gpio-cells = <2>; 375 compatible = "aspeed,ast2500-sgpio"; 376 gpio-controller; 377 interrupts = <40>; 378 reg = <0x1e780200 0x0100>; 379 clocks = <&syscon ASPEED_CLK_APB>; 380 #interrupt-cells = <2>; 381 interrupt-controller; 382 bus-frequency = <12000000>; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&pinctrl_sgpm_default>; 385 status = "disabled"; 386 }; 387 388 rtc: rtc@1e781000 { 389 compatible = "aspeed,ast2500-rtc"; 390 reg = <0x1e781000 0x18>; 391 status = "disabled"; 392 }; 393 394 timer: timer@1e782000 { 395 /* This timer is a Faraday FTTMR010 derivative */ 396 compatible = "aspeed,ast2400-timer"; 397 reg = <0x1e782000 0x90>; 398 interrupts = <16 17 18 35 36 37 38 39>; 399 clocks = <&syscon ASPEED_CLK_APB>; 400 clock-names = "PCLK"; 401 }; 402 403 uart1: serial@1e783000 { 404 compatible = "ns16550a"; 405 reg = <0x1e783000 0x20>; 406 reg-shift = <2>; 407 interrupts = <9>; 408 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; 409 resets = <&lpc_reset 4>; 410 no-loopback-test; 411 status = "disabled"; 412 }; 413 414 uart5: serial@1e784000 { 415 compatible = "ns16550a"; 416 reg = <0x1e784000 0x20>; 417 reg-shift = <2>; 418 interrupts = <10>; 419 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; 420 no-loopback-test; 421 status = "disabled"; 422 }; 423 424 wdt1: watchdog@1e785000 { 425 compatible = "aspeed,ast2500-wdt"; 426 reg = <0x1e785000 0x20>; 427 clocks = <&syscon ASPEED_CLK_APB>; 428 }; 429 430 wdt2: watchdog@1e785020 { 431 compatible = "aspeed,ast2500-wdt"; 432 reg = <0x1e785020 0x20>; 433 clocks = <&syscon ASPEED_CLK_APB>; 434 }; 435 436 wdt3: watchdog@1e785040 { 437 compatible = "aspeed,ast2500-wdt"; 438 reg = <0x1e785040 0x20>; 439 clocks = <&syscon ASPEED_CLK_APB>; 440 status = "disabled"; 441 }; 442 443 pwm_tacho: pwm-tacho-controller@1e786000 { 444 compatible = "aspeed,ast2500-pwm-tacho"; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 reg = <0x1e786000 0x1000>; 448 clocks = <&syscon ASPEED_CLK_24M>; 449 resets = <&syscon ASPEED_RESET_PWM>; 450 status = "disabled"; 451 }; 452 453 vuart: serial@1e787000 { 454 compatible = "aspeed,ast2500-vuart"; 455 reg = <0x1e787000 0x40>; 456 reg-shift = <2>; 457 interrupts = <8>; 458 clocks = <&syscon ASPEED_CLK_APB>; 459 no-loopback-test; 460 status = "disabled"; 461 }; 462 463 lpc: lpc@1e789000 { 464 compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"; 465 reg = <0x1e789000 0x1000>; 466 reg-io-width = <4>; 467 468 #address-cells = <1>; 469 #size-cells = <1>; 470 ranges = <0x0 0x1e789000 0x1000>; 471 472 kcs1: kcs@24 { 473 compatible = "aspeed,ast2500-kcs-bmc-v2"; 474 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; 475 interrupts = <8>; 476 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 477 status = "disabled"; 478 }; 479 480 kcs2: kcs@28 { 481 compatible = "aspeed,ast2500-kcs-bmc-v2"; 482 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; 483 interrupts = <8>; 484 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 485 status = "disabled"; 486 }; 487 488 kcs3: kcs@2c { 489 compatible = "aspeed,ast2500-kcs-bmc-v2"; 490 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; 491 interrupts = <8>; 492 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 493 status = "disabled"; 494 }; 495 496 kcs4: kcs@114 { 497 compatible = "aspeed,ast2500-kcs-bmc-v2"; 498 reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; 499 interrupts = <8>; 500 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 501 status = "disabled"; 502 }; 503 504 lpc_ctrl: lpc-ctrl@80 { 505 compatible = "aspeed,ast2500-lpc-ctrl"; 506 reg = <0x80 0x10>; 507 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 508 status = "disabled"; 509 }; 510 511 lpc_snoop: lpc-snoop@90 { 512 compatible = "aspeed,ast2500-lpc-snoop"; 513 reg = <0x90 0x8>; 514 interrupts = <8>; 515 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 516 status = "disabled"; 517 }; 518 519 lpc_reset: reset-controller@98 { 520 compatible = "aspeed,ast2500-lpc-reset"; 521 reg = <0x98 0x4>; 522 #reset-cells = <1>; 523 }; 524 525 uart_routing: uart-routing@9c { 526 compatible = "aspeed,ast2500-uart-routing"; 527 reg = <0x9c 0x4>; 528 status = "disabled"; 529 }; 530 531 lhc: lhc@a0 { 532 compatible = "aspeed,ast2500-lhc"; 533 reg = <0xa0 0x24 0xc8 0x8>; 534 }; 535 536 537 ibt: ibt@140 { 538 compatible = "aspeed,ast2500-ibt-bmc"; 539 reg = <0x140 0x18>; 540 interrupts = <8>; 541 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 542 status = "disabled"; 543 }; 544 }; 545 546 i2c: bus@1e78a000 { 547 compatible = "simple-bus"; 548 #address-cells = <1>; 549 #size-cells = <1>; 550 ranges = <0 0x1e78a000 0x1000>; 551 }; 552 553 peci0: peci-controller@1e78b000 { 554 compatible = "aspeed,ast2500-peci"; 555 reg = <0x1e78b000 0x60>; 556 interrupts = <15>; 557 clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; 558 resets = <&syscon ASPEED_RESET_PECI>; 559 cmd-timeout-ms = <1000>; 560 clock-frequency = <1000000>; 561 status = "disabled"; 562 }; 563 564 uart2: serial@1e78d000 { 565 compatible = "ns16550a"; 566 reg = <0x1e78d000 0x20>; 567 reg-shift = <2>; 568 interrupts = <32>; 569 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; 570 resets = <&lpc_reset 5>; 571 no-loopback-test; 572 status = "disabled"; 573 }; 574 575 uart3: serial@1e78e000 { 576 compatible = "ns16550a"; 577 reg = <0x1e78e000 0x20>; 578 reg-shift = <2>; 579 interrupts = <33>; 580 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; 581 resets = <&lpc_reset 6>; 582 no-loopback-test; 583 status = "disabled"; 584 }; 585 586 uart4: serial@1e78f000 { 587 compatible = "ns16550a"; 588 reg = <0x1e78f000 0x20>; 589 reg-shift = <2>; 590 interrupts = <34>; 591 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; 592 resets = <&lpc_reset 7>; 593 no-loopback-test; 594 status = "disabled"; 595 }; 596 }; 597 598 /* There's another APB mapping at 0x1e790000 for 0x00010000 */ 599 }; 600}; 601 602&i2c { 603 i2c_ic: interrupt-controller@0 { 604 #interrupt-cells = <1>; 605 compatible = "aspeed,ast2500-i2c-ic"; 606 reg = <0x0 0x40>; 607 interrupts = <12>; 608 interrupt-controller; 609 }; 610 611 i2c0: i2c@40 { 612 #address-cells = <1>; 613 #size-cells = <0>; 614 615 reg = <0x40 0x40>; 616 compatible = "aspeed,ast2500-i2c-bus"; 617 clocks = <&syscon ASPEED_CLK_APB>; 618 resets = <&syscon ASPEED_RESET_I2C>; 619 bus-frequency = <100000>; 620 interrupts = <0>; 621 interrupt-parent = <&i2c_ic>; 622 status = "disabled"; 623 /* Does not need pinctrl properties */ 624 }; 625 626 i2c1: i2c@80 { 627 #address-cells = <1>; 628 #size-cells = <0>; 629 630 reg = <0x80 0x40>; 631 compatible = "aspeed,ast2500-i2c-bus"; 632 clocks = <&syscon ASPEED_CLK_APB>; 633 resets = <&syscon ASPEED_RESET_I2C>; 634 bus-frequency = <100000>; 635 interrupts = <1>; 636 interrupt-parent = <&i2c_ic>; 637 status = "disabled"; 638 /* Does not need pinctrl properties */ 639 }; 640 641 i2c2: i2c@c0 { 642 #address-cells = <1>; 643 #size-cells = <0>; 644 645 reg = <0xc0 0x40>; 646 compatible = "aspeed,ast2500-i2c-bus"; 647 clocks = <&syscon ASPEED_CLK_APB>; 648 resets = <&syscon ASPEED_RESET_I2C>; 649 bus-frequency = <100000>; 650 interrupts = <2>; 651 interrupt-parent = <&i2c_ic>; 652 pinctrl-names = "default"; 653 pinctrl-0 = <&pinctrl_i2c3_default>; 654 status = "disabled"; 655 }; 656 657 i2c3: i2c@100 { 658 #address-cells = <1>; 659 #size-cells = <0>; 660 661 reg = <0x100 0x40>; 662 compatible = "aspeed,ast2500-i2c-bus"; 663 clocks = <&syscon ASPEED_CLK_APB>; 664 resets = <&syscon ASPEED_RESET_I2C>; 665 bus-frequency = <100000>; 666 interrupts = <3>; 667 interrupt-parent = <&i2c_ic>; 668 pinctrl-names = "default"; 669 pinctrl-0 = <&pinctrl_i2c4_default>; 670 status = "disabled"; 671 }; 672 673 i2c4: i2c@140 { 674 #address-cells = <1>; 675 #size-cells = <0>; 676 677 reg = <0x140 0x40>; 678 compatible = "aspeed,ast2500-i2c-bus"; 679 clocks = <&syscon ASPEED_CLK_APB>; 680 resets = <&syscon ASPEED_RESET_I2C>; 681 bus-frequency = <100000>; 682 interrupts = <4>; 683 interrupt-parent = <&i2c_ic>; 684 pinctrl-names = "default"; 685 pinctrl-0 = <&pinctrl_i2c5_default>; 686 status = "disabled"; 687 }; 688 689 i2c5: i2c@180 { 690 #address-cells = <1>; 691 #size-cells = <0>; 692 693 reg = <0x180 0x40>; 694 compatible = "aspeed,ast2500-i2c-bus"; 695 clocks = <&syscon ASPEED_CLK_APB>; 696 resets = <&syscon ASPEED_RESET_I2C>; 697 bus-frequency = <100000>; 698 interrupts = <5>; 699 interrupt-parent = <&i2c_ic>; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&pinctrl_i2c6_default>; 702 status = "disabled"; 703 }; 704 705 i2c6: i2c@1c0 { 706 #address-cells = <1>; 707 #size-cells = <0>; 708 709 reg = <0x1c0 0x40>; 710 compatible = "aspeed,ast2500-i2c-bus"; 711 clocks = <&syscon ASPEED_CLK_APB>; 712 resets = <&syscon ASPEED_RESET_I2C>; 713 bus-frequency = <100000>; 714 interrupts = <6>; 715 interrupt-parent = <&i2c_ic>; 716 pinctrl-names = "default"; 717 pinctrl-0 = <&pinctrl_i2c7_default>; 718 status = "disabled"; 719 }; 720 721 i2c7: i2c@300 { 722 #address-cells = <1>; 723 #size-cells = <0>; 724 725 reg = <0x300 0x40>; 726 compatible = "aspeed,ast2500-i2c-bus"; 727 clocks = <&syscon ASPEED_CLK_APB>; 728 resets = <&syscon ASPEED_RESET_I2C>; 729 bus-frequency = <100000>; 730 interrupts = <7>; 731 interrupt-parent = <&i2c_ic>; 732 pinctrl-names = "default"; 733 pinctrl-0 = <&pinctrl_i2c8_default>; 734 status = "disabled"; 735 }; 736 737 i2c8: i2c@340 { 738 #address-cells = <1>; 739 #size-cells = <0>; 740 741 reg = <0x340 0x40>; 742 compatible = "aspeed,ast2500-i2c-bus"; 743 clocks = <&syscon ASPEED_CLK_APB>; 744 resets = <&syscon ASPEED_RESET_I2C>; 745 bus-frequency = <100000>; 746 interrupts = <8>; 747 interrupt-parent = <&i2c_ic>; 748 pinctrl-names = "default"; 749 pinctrl-0 = <&pinctrl_i2c9_default>; 750 status = "disabled"; 751 }; 752 753 i2c9: i2c@380 { 754 #address-cells = <1>; 755 #size-cells = <0>; 756 757 reg = <0x380 0x40>; 758 compatible = "aspeed,ast2500-i2c-bus"; 759 clocks = <&syscon ASPEED_CLK_APB>; 760 resets = <&syscon ASPEED_RESET_I2C>; 761 bus-frequency = <100000>; 762 interrupts = <9>; 763 interrupt-parent = <&i2c_ic>; 764 pinctrl-names = "default"; 765 pinctrl-0 = <&pinctrl_i2c10_default>; 766 status = "disabled"; 767 }; 768 769 i2c10: i2c@3c0 { 770 #address-cells = <1>; 771 #size-cells = <0>; 772 773 reg = <0x3c0 0x40>; 774 compatible = "aspeed,ast2500-i2c-bus"; 775 clocks = <&syscon ASPEED_CLK_APB>; 776 resets = <&syscon ASPEED_RESET_I2C>; 777 bus-frequency = <100000>; 778 interrupts = <10>; 779 interrupt-parent = <&i2c_ic>; 780 pinctrl-names = "default"; 781 pinctrl-0 = <&pinctrl_i2c11_default>; 782 status = "disabled"; 783 }; 784 785 i2c11: i2c@400 { 786 #address-cells = <1>; 787 #size-cells = <0>; 788 789 reg = <0x400 0x40>; 790 compatible = "aspeed,ast2500-i2c-bus"; 791 clocks = <&syscon ASPEED_CLK_APB>; 792 resets = <&syscon ASPEED_RESET_I2C>; 793 bus-frequency = <100000>; 794 interrupts = <11>; 795 interrupt-parent = <&i2c_ic>; 796 pinctrl-names = "default"; 797 pinctrl-0 = <&pinctrl_i2c12_default>; 798 status = "disabled"; 799 }; 800 801 i2c12: i2c@440 { 802 #address-cells = <1>; 803 #size-cells = <0>; 804 805 reg = <0x440 0x40>; 806 compatible = "aspeed,ast2500-i2c-bus"; 807 clocks = <&syscon ASPEED_CLK_APB>; 808 resets = <&syscon ASPEED_RESET_I2C>; 809 bus-frequency = <100000>; 810 interrupts = <12>; 811 interrupt-parent = <&i2c_ic>; 812 pinctrl-names = "default"; 813 pinctrl-0 = <&pinctrl_i2c13_default>; 814 status = "disabled"; 815 }; 816 817 i2c13: i2c@480 { 818 #address-cells = <1>; 819 #size-cells = <0>; 820 821 reg = <0x480 0x40>; 822 compatible = "aspeed,ast2500-i2c-bus"; 823 clocks = <&syscon ASPEED_CLK_APB>; 824 resets = <&syscon ASPEED_RESET_I2C>; 825 bus-frequency = <100000>; 826 interrupts = <13>; 827 interrupt-parent = <&i2c_ic>; 828 pinctrl-names = "default"; 829 pinctrl-0 = <&pinctrl_i2c14_default>; 830 status = "disabled"; 831 }; 832}; 833 834&pinctrl { 835 pinctrl_acpi_default: acpi_default { 836 function = "ACPI"; 837 groups = "ACPI"; 838 }; 839 840 pinctrl_adc0_default: adc0_default { 841 function = "ADC0"; 842 groups = "ADC0"; 843 }; 844 845 pinctrl_adc1_default: adc1_default { 846 function = "ADC1"; 847 groups = "ADC1"; 848 }; 849 850 pinctrl_adc10_default: adc10_default { 851 function = "ADC10"; 852 groups = "ADC10"; 853 }; 854 855 pinctrl_adc11_default: adc11_default { 856 function = "ADC11"; 857 groups = "ADC11"; 858 }; 859 860 pinctrl_adc12_default: adc12_default { 861 function = "ADC12"; 862 groups = "ADC12"; 863 }; 864 865 pinctrl_adc13_default: adc13_default { 866 function = "ADC13"; 867 groups = "ADC13"; 868 }; 869 870 pinctrl_adc14_default: adc14_default { 871 function = "ADC14"; 872 groups = "ADC14"; 873 }; 874 875 pinctrl_adc15_default: adc15_default { 876 function = "ADC15"; 877 groups = "ADC15"; 878 }; 879 880 pinctrl_adc2_default: adc2_default { 881 function = "ADC2"; 882 groups = "ADC2"; 883 }; 884 885 pinctrl_adc3_default: adc3_default { 886 function = "ADC3"; 887 groups = "ADC3"; 888 }; 889 890 pinctrl_adc4_default: adc4_default { 891 function = "ADC4"; 892 groups = "ADC4"; 893 }; 894 895 pinctrl_adc5_default: adc5_default { 896 function = "ADC5"; 897 groups = "ADC5"; 898 }; 899 900 pinctrl_adc6_default: adc6_default { 901 function = "ADC6"; 902 groups = "ADC6"; 903 }; 904 905 pinctrl_adc7_default: adc7_default { 906 function = "ADC7"; 907 groups = "ADC7"; 908 }; 909 910 pinctrl_adc8_default: adc8_default { 911 function = "ADC8"; 912 groups = "ADC8"; 913 }; 914 915 pinctrl_adc9_default: adc9_default { 916 function = "ADC9"; 917 groups = "ADC9"; 918 }; 919 920 pinctrl_bmcint_default: bmcint_default { 921 function = "BMCINT"; 922 groups = "BMCINT"; 923 }; 924 925 pinctrl_ddcclk_default: ddcclk_default { 926 function = "DDCCLK"; 927 groups = "DDCCLK"; 928 }; 929 930 pinctrl_ddcdat_default: ddcdat_default { 931 function = "DDCDAT"; 932 groups = "DDCDAT"; 933 }; 934 935 pinctrl_espi_default: espi_default { 936 function = "ESPI"; 937 groups = "ESPI"; 938 }; 939 940 pinctrl_fwspics1_default: fwspics1_default { 941 function = "FWSPICS1"; 942 groups = "FWSPICS1"; 943 }; 944 945 pinctrl_fwspics2_default: fwspics2_default { 946 function = "FWSPICS2"; 947 groups = "FWSPICS2"; 948 }; 949 950 pinctrl_gpid0_default: gpid0_default { 951 function = "GPID0"; 952 groups = "GPID0"; 953 }; 954 955 pinctrl_gpid2_default: gpid2_default { 956 function = "GPID2"; 957 groups = "GPID2"; 958 }; 959 960 pinctrl_gpid4_default: gpid4_default { 961 function = "GPID4"; 962 groups = "GPID4"; 963 }; 964 965 pinctrl_gpid6_default: gpid6_default { 966 function = "GPID6"; 967 groups = "GPID6"; 968 }; 969 970 pinctrl_gpie0_default: gpie0_default { 971 function = "GPIE0"; 972 groups = "GPIE0"; 973 }; 974 975 pinctrl_gpie2_default: gpie2_default { 976 function = "GPIE2"; 977 groups = "GPIE2"; 978 }; 979 980 pinctrl_gpie4_default: gpie4_default { 981 function = "GPIE4"; 982 groups = "GPIE4"; 983 }; 984 985 pinctrl_gpie6_default: gpie6_default { 986 function = "GPIE6"; 987 groups = "GPIE6"; 988 }; 989 990 pinctrl_i2c10_default: i2c10_default { 991 function = "I2C10"; 992 groups = "I2C10"; 993 }; 994 995 pinctrl_i2c11_default: i2c11_default { 996 function = "I2C11"; 997 groups = "I2C11"; 998 }; 999 1000 pinctrl_i2c12_default: i2c12_default { 1001 function = "I2C12"; 1002 groups = "I2C12"; 1003 }; 1004 1005 pinctrl_i2c13_default: i2c13_default { 1006 function = "I2C13"; 1007 groups = "I2C13"; 1008 }; 1009 1010 pinctrl_i2c14_default: i2c14_default { 1011 function = "I2C14"; 1012 groups = "I2C14"; 1013 }; 1014 1015 pinctrl_i2c3_default: i2c3_default { 1016 function = "I2C3"; 1017 groups = "I2C3"; 1018 }; 1019 1020 pinctrl_i2c4_default: i2c4_default { 1021 function = "I2C4"; 1022 groups = "I2C4"; 1023 }; 1024 1025 pinctrl_i2c5_default: i2c5_default { 1026 function = "I2C5"; 1027 groups = "I2C5"; 1028 }; 1029 1030 pinctrl_i2c6_default: i2c6_default { 1031 function = "I2C6"; 1032 groups = "I2C6"; 1033 }; 1034 1035 pinctrl_i2c7_default: i2c7_default { 1036 function = "I2C7"; 1037 groups = "I2C7"; 1038 }; 1039 1040 pinctrl_i2c8_default: i2c8_default { 1041 function = "I2C8"; 1042 groups = "I2C8"; 1043 }; 1044 1045 pinctrl_i2c9_default: i2c9_default { 1046 function = "I2C9"; 1047 groups = "I2C9"; 1048 }; 1049 1050 pinctrl_lad0_default: lad0_default { 1051 function = "LAD0"; 1052 groups = "LAD0"; 1053 }; 1054 1055 pinctrl_lad1_default: lad1_default { 1056 function = "LAD1"; 1057 groups = "LAD1"; 1058 }; 1059 1060 pinctrl_lad2_default: lad2_default { 1061 function = "LAD2"; 1062 groups = "LAD2"; 1063 }; 1064 1065 pinctrl_lad3_default: lad3_default { 1066 function = "LAD3"; 1067 groups = "LAD3"; 1068 }; 1069 1070 pinctrl_lclk_default: lclk_default { 1071 function = "LCLK"; 1072 groups = "LCLK"; 1073 }; 1074 1075 pinctrl_lframe_default: lframe_default { 1076 function = "LFRAME"; 1077 groups = "LFRAME"; 1078 }; 1079 1080 pinctrl_lpchc_default: lpchc_default { 1081 function = "LPCHC"; 1082 groups = "LPCHC"; 1083 }; 1084 1085 pinctrl_lpcpd_default: lpcpd_default { 1086 function = "LPCPD"; 1087 groups = "LPCPD"; 1088 }; 1089 1090 pinctrl_lpcplus_default: lpcplus_default { 1091 function = "LPCPLUS"; 1092 groups = "LPCPLUS"; 1093 }; 1094 1095 pinctrl_lpcpme_default: lpcpme_default { 1096 function = "LPCPME"; 1097 groups = "LPCPME"; 1098 }; 1099 1100 pinctrl_lpcrst_default: lpcrst_default { 1101 function = "LPCRST"; 1102 groups = "LPCRST"; 1103 }; 1104 1105 pinctrl_lpcsmi_default: lpcsmi_default { 1106 function = "LPCSMI"; 1107 groups = "LPCSMI"; 1108 }; 1109 1110 pinctrl_lsirq_default: lsirq_default { 1111 function = "LSIRQ"; 1112 groups = "LSIRQ"; 1113 }; 1114 1115 pinctrl_mac1link_default: mac1link_default { 1116 function = "MAC1LINK"; 1117 groups = "MAC1LINK"; 1118 }; 1119 1120 pinctrl_mac2link_default: mac2link_default { 1121 function = "MAC2LINK"; 1122 groups = "MAC2LINK"; 1123 }; 1124 1125 pinctrl_mdio1_default: mdio1_default { 1126 function = "MDIO1"; 1127 groups = "MDIO1"; 1128 }; 1129 1130 pinctrl_mdio2_default: mdio2_default { 1131 function = "MDIO2"; 1132 groups = "MDIO2"; 1133 }; 1134 1135 pinctrl_ncts1_default: ncts1_default { 1136 function = "NCTS1"; 1137 groups = "NCTS1"; 1138 }; 1139 1140 pinctrl_ncts2_default: ncts2_default { 1141 function = "NCTS2"; 1142 groups = "NCTS2"; 1143 }; 1144 1145 pinctrl_ncts3_default: ncts3_default { 1146 function = "NCTS3"; 1147 groups = "NCTS3"; 1148 }; 1149 1150 pinctrl_ncts4_default: ncts4_default { 1151 function = "NCTS4"; 1152 groups = "NCTS4"; 1153 }; 1154 1155 pinctrl_ndcd1_default: ndcd1_default { 1156 function = "NDCD1"; 1157 groups = "NDCD1"; 1158 }; 1159 1160 pinctrl_ndcd2_default: ndcd2_default { 1161 function = "NDCD2"; 1162 groups = "NDCD2"; 1163 }; 1164 1165 pinctrl_ndcd3_default: ndcd3_default { 1166 function = "NDCD3"; 1167 groups = "NDCD3"; 1168 }; 1169 1170 pinctrl_ndcd4_default: ndcd4_default { 1171 function = "NDCD4"; 1172 groups = "NDCD4"; 1173 }; 1174 1175 pinctrl_ndsr1_default: ndsr1_default { 1176 function = "NDSR1"; 1177 groups = "NDSR1"; 1178 }; 1179 1180 pinctrl_ndsr2_default: ndsr2_default { 1181 function = "NDSR2"; 1182 groups = "NDSR2"; 1183 }; 1184 1185 pinctrl_ndsr3_default: ndsr3_default { 1186 function = "NDSR3"; 1187 groups = "NDSR3"; 1188 }; 1189 1190 pinctrl_ndsr4_default: ndsr4_default { 1191 function = "NDSR4"; 1192 groups = "NDSR4"; 1193 }; 1194 1195 pinctrl_ndtr1_default: ndtr1_default { 1196 function = "NDTR1"; 1197 groups = "NDTR1"; 1198 }; 1199 1200 pinctrl_ndtr2_default: ndtr2_default { 1201 function = "NDTR2"; 1202 groups = "NDTR2"; 1203 }; 1204 1205 pinctrl_ndtr3_default: ndtr3_default { 1206 function = "NDTR3"; 1207 groups = "NDTR3"; 1208 }; 1209 1210 pinctrl_ndtr4_default: ndtr4_default { 1211 function = "NDTR4"; 1212 groups = "NDTR4"; 1213 }; 1214 1215 pinctrl_nri1_default: nri1_default { 1216 function = "NRI1"; 1217 groups = "NRI1"; 1218 }; 1219 1220 pinctrl_nri2_default: nri2_default { 1221 function = "NRI2"; 1222 groups = "NRI2"; 1223 }; 1224 1225 pinctrl_nri3_default: nri3_default { 1226 function = "NRI3"; 1227 groups = "NRI3"; 1228 }; 1229 1230 pinctrl_nri4_default: nri4_default { 1231 function = "NRI4"; 1232 groups = "NRI4"; 1233 }; 1234 1235 pinctrl_nrts1_default: nrts1_default { 1236 function = "NRTS1"; 1237 groups = "NRTS1"; 1238 }; 1239 1240 pinctrl_nrts2_default: nrts2_default { 1241 function = "NRTS2"; 1242 groups = "NRTS2"; 1243 }; 1244 1245 pinctrl_nrts3_default: nrts3_default { 1246 function = "NRTS3"; 1247 groups = "NRTS3"; 1248 }; 1249 1250 pinctrl_nrts4_default: nrts4_default { 1251 function = "NRTS4"; 1252 groups = "NRTS4"; 1253 }; 1254 1255 pinctrl_oscclk_default: oscclk_default { 1256 function = "OSCCLK"; 1257 groups = "OSCCLK"; 1258 }; 1259 1260 pinctrl_pewake_default: pewake_default { 1261 function = "PEWAKE"; 1262 groups = "PEWAKE"; 1263 }; 1264 1265 pinctrl_pnor_default: pnor_default { 1266 function = "PNOR"; 1267 groups = "PNOR"; 1268 }; 1269 1270 pinctrl_pwm0_default: pwm0_default { 1271 function = "PWM0"; 1272 groups = "PWM0"; 1273 }; 1274 1275 pinctrl_pwm1_default: pwm1_default { 1276 function = "PWM1"; 1277 groups = "PWM1"; 1278 }; 1279 1280 pinctrl_pwm2_default: pwm2_default { 1281 function = "PWM2"; 1282 groups = "PWM2"; 1283 }; 1284 1285 pinctrl_pwm3_default: pwm3_default { 1286 function = "PWM3"; 1287 groups = "PWM3"; 1288 }; 1289 1290 pinctrl_pwm4_default: pwm4_default { 1291 function = "PWM4"; 1292 groups = "PWM4"; 1293 }; 1294 1295 pinctrl_pwm5_default: pwm5_default { 1296 function = "PWM5"; 1297 groups = "PWM5"; 1298 }; 1299 1300 pinctrl_pwm6_default: pwm6_default { 1301 function = "PWM6"; 1302 groups = "PWM6"; 1303 }; 1304 1305 pinctrl_pwm7_default: pwm7_default { 1306 function = "PWM7"; 1307 groups = "PWM7"; 1308 }; 1309 1310 pinctrl_rgmii1_default: rgmii1_default { 1311 function = "RGMII1"; 1312 groups = "RGMII1"; 1313 }; 1314 1315 pinctrl_rgmii2_default: rgmii2_default { 1316 function = "RGMII2"; 1317 groups = "RGMII2"; 1318 }; 1319 1320 pinctrl_rmii1_default: rmii1_default { 1321 function = "RMII1"; 1322 groups = "RMII1"; 1323 }; 1324 1325 pinctrl_rmii2_default: rmii2_default { 1326 function = "RMII2"; 1327 groups = "RMII2"; 1328 }; 1329 1330 pinctrl_rxd1_default: rxd1_default { 1331 function = "RXD1"; 1332 groups = "RXD1"; 1333 }; 1334 1335 pinctrl_rxd2_default: rxd2_default { 1336 function = "RXD2"; 1337 groups = "RXD2"; 1338 }; 1339 1340 pinctrl_rxd3_default: rxd3_default { 1341 function = "RXD3"; 1342 groups = "RXD3"; 1343 }; 1344 1345 pinctrl_rxd4_default: rxd4_default { 1346 function = "RXD4"; 1347 groups = "RXD4"; 1348 }; 1349 1350 pinctrl_salt1_default: salt1_default { 1351 function = "SALT1"; 1352 groups = "SALT1"; 1353 }; 1354 1355 pinctrl_salt10_default: salt10_default { 1356 function = "SALT10"; 1357 groups = "SALT10"; 1358 }; 1359 1360 pinctrl_salt11_default: salt11_default { 1361 function = "SALT11"; 1362 groups = "SALT11"; 1363 }; 1364 1365 pinctrl_salt12_default: salt12_default { 1366 function = "SALT12"; 1367 groups = "SALT12"; 1368 }; 1369 1370 pinctrl_salt13_default: salt13_default { 1371 function = "SALT13"; 1372 groups = "SALT13"; 1373 }; 1374 1375 pinctrl_salt14_default: salt14_default { 1376 function = "SALT14"; 1377 groups = "SALT14"; 1378 }; 1379 1380 pinctrl_salt2_default: salt2_default { 1381 function = "SALT2"; 1382 groups = "SALT2"; 1383 }; 1384 1385 pinctrl_salt3_default: salt3_default { 1386 function = "SALT3"; 1387 groups = "SALT3"; 1388 }; 1389 1390 pinctrl_salt4_default: salt4_default { 1391 function = "SALT4"; 1392 groups = "SALT4"; 1393 }; 1394 1395 pinctrl_salt5_default: salt5_default { 1396 function = "SALT5"; 1397 groups = "SALT5"; 1398 }; 1399 1400 pinctrl_salt6_default: salt6_default { 1401 function = "SALT6"; 1402 groups = "SALT6"; 1403 }; 1404 1405 pinctrl_salt7_default: salt7_default { 1406 function = "SALT7"; 1407 groups = "SALT7"; 1408 }; 1409 1410 pinctrl_salt8_default: salt8_default { 1411 function = "SALT8"; 1412 groups = "SALT8"; 1413 }; 1414 1415 pinctrl_salt9_default: salt9_default { 1416 function = "SALT9"; 1417 groups = "SALT9"; 1418 }; 1419 1420 pinctrl_scl1_default: scl1_default { 1421 function = "SCL1"; 1422 groups = "SCL1"; 1423 }; 1424 1425 pinctrl_scl2_default: scl2_default { 1426 function = "SCL2"; 1427 groups = "SCL2"; 1428 }; 1429 1430 pinctrl_sd1_default: sd1_default { 1431 function = "SD1"; 1432 groups = "SD1"; 1433 }; 1434 1435 pinctrl_sd2_default: sd2_default { 1436 function = "SD2"; 1437 groups = "SD2"; 1438 }; 1439 1440 pinctrl_sda1_default: sda1_default { 1441 function = "SDA1"; 1442 groups = "SDA1"; 1443 }; 1444 1445 pinctrl_sda2_default: sda2_default { 1446 function = "SDA2"; 1447 groups = "SDA2"; 1448 }; 1449 1450 pinctrl_sgpm_default: sgpm_default { 1451 function = "SGPM"; 1452 groups = "SGPM"; 1453 }; 1454 1455 pinctrl_sgps1_default: sgps1_default { 1456 function = "SGPS1"; 1457 groups = "SGPS1"; 1458 }; 1459 1460 pinctrl_sgps2_default: sgps2_default { 1461 function = "SGPS2"; 1462 groups = "SGPS2"; 1463 }; 1464 1465 pinctrl_sioonctrl_default: sioonctrl_default { 1466 function = "SIOONCTRL"; 1467 groups = "SIOONCTRL"; 1468 }; 1469 1470 pinctrl_siopbi_default: siopbi_default { 1471 function = "SIOPBI"; 1472 groups = "SIOPBI"; 1473 }; 1474 1475 pinctrl_siopbo_default: siopbo_default { 1476 function = "SIOPBO"; 1477 groups = "SIOPBO"; 1478 }; 1479 1480 pinctrl_siopwreq_default: siopwreq_default { 1481 function = "SIOPWREQ"; 1482 groups = "SIOPWREQ"; 1483 }; 1484 1485 pinctrl_siopwrgd_default: siopwrgd_default { 1486 function = "SIOPWRGD"; 1487 groups = "SIOPWRGD"; 1488 }; 1489 1490 pinctrl_sios3_default: sios3_default { 1491 function = "SIOS3"; 1492 groups = "SIOS3"; 1493 }; 1494 1495 pinctrl_sios5_default: sios5_default { 1496 function = "SIOS5"; 1497 groups = "SIOS5"; 1498 }; 1499 1500 pinctrl_siosci_default: siosci_default { 1501 function = "SIOSCI"; 1502 groups = "SIOSCI"; 1503 }; 1504 1505 pinctrl_spi1_default: spi1_default { 1506 function = "SPI1"; 1507 groups = "SPI1"; 1508 }; 1509 1510 pinctrl_spi1cs1_default: spi1cs1_default { 1511 function = "SPI1CS1"; 1512 groups = "SPI1CS1"; 1513 }; 1514 1515 pinctrl_spi1debug_default: spi1debug_default { 1516 function = "SPI1DEBUG"; 1517 groups = "SPI1DEBUG"; 1518 }; 1519 1520 pinctrl_spi1passthru_default: spi1passthru_default { 1521 function = "SPI1PASSTHRU"; 1522 groups = "SPI1PASSTHRU"; 1523 }; 1524 1525 pinctrl_spi2ck_default: spi2ck_default { 1526 function = "SPI2CK"; 1527 groups = "SPI2CK"; 1528 }; 1529 1530 pinctrl_spi2cs0_default: spi2cs0_default { 1531 function = "SPI2CS0"; 1532 groups = "SPI2CS0"; 1533 }; 1534 1535 pinctrl_spi2cs1_default: spi2cs1_default { 1536 function = "SPI2CS1"; 1537 groups = "SPI2CS1"; 1538 }; 1539 1540 pinctrl_spi2miso_default: spi2miso_default { 1541 function = "SPI2MISO"; 1542 groups = "SPI2MISO"; 1543 }; 1544 1545 pinctrl_spi2mosi_default: spi2mosi_default { 1546 function = "SPI2MOSI"; 1547 groups = "SPI2MOSI"; 1548 }; 1549 1550 pinctrl_timer3_default: timer3_default { 1551 function = "TIMER3"; 1552 groups = "TIMER3"; 1553 }; 1554 1555 pinctrl_timer4_default: timer4_default { 1556 function = "TIMER4"; 1557 groups = "TIMER4"; 1558 }; 1559 1560 pinctrl_timer5_default: timer5_default { 1561 function = "TIMER5"; 1562 groups = "TIMER5"; 1563 }; 1564 1565 pinctrl_timer6_default: timer6_default { 1566 function = "TIMER6"; 1567 groups = "TIMER6"; 1568 }; 1569 1570 pinctrl_timer7_default: timer7_default { 1571 function = "TIMER7"; 1572 groups = "TIMER7"; 1573 }; 1574 1575 pinctrl_timer8_default: timer8_default { 1576 function = "TIMER8"; 1577 groups = "TIMER8"; 1578 }; 1579 1580 pinctrl_txd1_default: txd1_default { 1581 function = "TXD1"; 1582 groups = "TXD1"; 1583 }; 1584 1585 pinctrl_txd2_default: txd2_default { 1586 function = "TXD2"; 1587 groups = "TXD2"; 1588 }; 1589 1590 pinctrl_txd3_default: txd3_default { 1591 function = "TXD3"; 1592 groups = "TXD3"; 1593 }; 1594 1595 pinctrl_txd4_default: txd4_default { 1596 function = "TXD4"; 1597 groups = "TXD4"; 1598 }; 1599 1600 pinctrl_uart6_default: uart6_default { 1601 function = "UART6"; 1602 groups = "UART6"; 1603 }; 1604 1605 pinctrl_usbcki_default: usbcki_default { 1606 function = "USBCKI"; 1607 groups = "USBCKI"; 1608 }; 1609 1610 pinctrl_usb2ah_default: usb2ah_default { 1611 function = "USB2AH"; 1612 groups = "USB2AH"; 1613 }; 1614 1615 pinctrl_usb2ad_default: usb2ad_default { 1616 function = "USB2AD"; 1617 groups = "USB2AD"; 1618 }; 1619 1620 pinctrl_usb11bhid_default: usb11bhid_default { 1621 function = "USB11BHID"; 1622 groups = "USB11BHID"; 1623 }; 1624 1625 pinctrl_usb2bh_default: usb2bh_default { 1626 function = "USB2BH"; 1627 groups = "USB2BH"; 1628 }; 1629 1630 pinctrl_vgabiosrom_default: vgabiosrom_default { 1631 function = "VGABIOSROM"; 1632 groups = "VGABIOSROM"; 1633 }; 1634 1635 pinctrl_vgahs_default: vgahs_default { 1636 function = "VGAHS"; 1637 groups = "VGAHS"; 1638 }; 1639 1640 pinctrl_vgavs_default: vgavs_default { 1641 function = "VGAVS"; 1642 groups = "VGAVS"; 1643 }; 1644 1645 pinctrl_vpi24_default: vpi24_default { 1646 function = "VPI24"; 1647 groups = "VPI24"; 1648 }; 1649 1650 pinctrl_vpo_default: vpo_default { 1651 function = "VPO"; 1652 groups = "VPO"; 1653 }; 1654 1655 pinctrl_wdtrst1_default: wdtrst1_default { 1656 function = "WDTRST1"; 1657 groups = "WDTRST1"; 1658 }; 1659 1660 pinctrl_wdtrst2_default: wdtrst2_default { 1661 function = "WDTRST2"; 1662 groups = "WDTRST2"; 1663 }; 1664}; 1665