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Revision tags: v9.2.2, v9.2.1, v9.2.0, v9.1.2, v9.1.1, v9.1.0, v8.0.0, v7.2.0 |
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| #
249497cb |
| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L
168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge)
1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L
168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge)
1E6E:D200-1E6E:D3FF PCIe Host Controller (RC)
1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller
6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
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Revision tags: v7.0.0, v6.2.0, v6.1.0 |
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| #
1d8b089d |
| 07-Apr-2021 |
Cédric Le Goater <clg@kaod.org> |
hw/misc: Add an iBT device model
Implement an IPMI BT interface model using a chardev backend to
communicate with an external PowerNV machine. It uses the OpenIPMI
simulator protocol for virtual mac
hw/misc: Add an iBT device model
Implement an IPMI BT interface model using a chardev backend to
communicate with an external PowerNV machine. It uses the OpenIPMI
simulator protocol for virtual machines described in :
https://github.com/cminyard/openipmi/blob/master/lanserv/README.vm
and implemented by the 'ipmi-bmc-extern' model on the host side.
To use, start the Aspeed BMC machine with :
-chardev socket,id=ipmi0,host=localhost,port=9002,ipv4,server,nowait \
-global driver=aspeed.ibt,property=chardev,value=ipmi0
and the PowerNV machine with :
-chardev socket,id=ipmi0,host=localhost,port=9002,reconnect=10 \
-device ipmi-bmc-extern,id=bmc0,chardev=ipmi0 \
-device isa-ipmi-bt,bmc=bmc0,irq=10 -nodefaults
Cc: Hao Wu <wuhaotsh@google.com>
Cc: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
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Revision tags: v5.2.0, v5.0.0, v4.2.0, v4.0.0, v4.0.0-rc1, v4.0.0-rc0, v3.1.0, v3.1.0-rc5, v3.1.0-rc4, v3.1.0-rc3, v3.1.0-rc2, v3.1.0-rc1, v3.1.0-rc0, libfdt-20181002, ppc-for-3.1-20180925, ppc-for-3.1-20180907, ppc-for-3.1-20180821, v3.0.0, v3.0.0-rc4, v2.12.1, ppc-for-3.0-20180801, v3.0.0-rc3, v3.0.0-rc2, v3.0.0-rc1, ppc-for-3.0-20180716, v3.0.0-rc0, ppc-for-3.0-20180709, ppc-for-3.0-20180703, v2.11.2, ppc-for-3.0-20180622, ppc-for-3.0-20180618, ppc-for-3.0-20180612, ppc-for-2.13-20180504, ppc-for-2.13-20180427, v2.12.0, v2.12.0-rc4, v2.12.0-rc3, ppc-for-2.12-20180410, v2.12.0-rc2, v2.12.0-rc1, v2.12.0-rc0, ppc-for-2.12-20180319, ppc-for-2.12-20180315, ppc-for-2.12-20180306, ppc-for-2.12-20180302, ppc-for-2.12-20180216, v2.11.1, ppc-for-2.12-20180212, ppc-for-2.12-20180129, ppc-for-2.12-20180121, ppc-for-2.12-20180119, ppc-for-2.12-20180117, ppc-for-2.12-20180111, ppc-for-2.12-20180108, ppc-for-2.12-20180103, ppc-for-2.12-20171219, v2.10.2, ppc-for-2.12-20171215, v2.11.0, v2.11.0-rc5, v2.11.0-rc4, ppc-for-2.11-20171205, ppc-for-2.11-20171204, v2.11.0-rc3 |
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| #
83b17b40 |
| 27-Nov-2017 |
Cédric Le Goater <clg@kaod.org> |
hw/misc: Add basic Aspeed PWM model
Just enough to quiet down the output when running with the logs.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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| #
923a00e8 |
| 19-Jan-2023 |
Joel Stanley <joel@jms.id.au> |
hw/misc: Add basic Aspeed GFX model
Enough model to capture the pinmux writes to enable correct operation of
the parts of pinmux that depend on GFX registers.
Signed-off-by: Joel Stanley <joel@jms.
hw/misc: Add basic Aspeed GFX model
Enough model to capture the pinmux writes to enable correct operation of
the parts of pinmux that depend on GFX registers.
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
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| #
78a75529 |
| 18-Oct-2021 |
Cédric Le Goater <clg@kaod.org> |
aspeed/smc: Improve support for the alternate boot function
Map the WDT2 registers in the AST2600 FMC memory region by creating a
local address space on top of WDT2 memory region.
The model only im
aspeed/smc: Improve support for the alternate boot function
Map the WDT2 registers in the AST2600 FMC memory region by creating a
local address space on top of WDT2 memory region.
The model only implements the enable bit of the control register. The
reload register uses a 0.1s unit instead of a 1us. Values are
converted on the fly when doing the accesses. The restart register is
the same.
TODO: This needs a rework since the FMC WDT2 device is an independent
watchdog logic embedded in the FMC device.
Cc: Peter Delevoryas <pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
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| #
338bb9b5 |
| 18-Oct-2021 |
Cédric Le Goater <clg@kaod.org> |
aspeed: Initialize the watchdog device models before the FMC models
Next changes will map the WDT2 registers in the AST2600 FMC memory
region. Make sure the MemoryRegion pointers are correctly initi
aspeed: Initialize the watchdog device models before the FMC models
Next changes will map the WDT2 registers in the AST2600 FMC memory
region. Make sure the MemoryRegion pointers are correctly initialized
before setting the object links.
Do the same in the Aspeed AST2400 and AST2500 SoC models for
consistency.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
show more ...
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| #
e0491ce0 |
| 12-Nov-2024 |
Guenter Roeck <linux@roeck-us.net> |
aspeed: Add uhci support for ast2600
Add UHCI support for the ast2600 SoC. With this patch, UHCI support
is successfully enabled on the rainier-bmc and ast2600-evb machines.
Signed-off-by: Guenter
aspeed: Add uhci support for ast2600
Add UHCI support for the ast2600 SoC. With this patch, UHCI support
is successfully enabled on the rainier-bmc and ast2600-evb machines.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
show more ...
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| #
b303cd14 |
| 04-Dec-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers
Currently, it set the hardcode value of capability registers to all ASPEED SOCs
However, the value of capab
hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers
Currently, it set the hardcode value of capability registers to all ASPEED SOCs
However, the value of capability registers should be different for all ASPEED
SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for
64-bits System Bus support for AST2700.
Introduce a new "capareg" class member whose data type is uint_64 to set the
different Capability Registers to all ASPEED SOCs.
The value of Capability Register is "0x0000000001e80080" for AST2400 and
AST2500. The value of Capability Register is "0x0000000701f80080" for AST2600.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
show more ...
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| #
99de4b63 |
| 04-Dec-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/arm/aspeed: Fix coding style
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
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| #
7e1e49d7 |
| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L
168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge)
1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L
168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge)
1E6E:D200-1E6E:D3FF PCIe Host Controller (RC)
1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller
6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
| #
cf4d96e9 |
| 07-Apr-2021 |
Cédric Le Goater <clg@kaod.org> |
hw/misc: Add an iBT device model
Implement an IPMI BT interface model using a chardev backend to
communicate with an external PowerNV machine. It uses the OpenIPMI
simulator protocol for virtual mac
hw/misc: Add an iBT device model
Implement an IPMI BT interface model using a chardev backend to
communicate with an external PowerNV machine. It uses the OpenIPMI
simulator protocol for virtual machines described in :
https://github.com/cminyard/openipmi/blob/master/lanserv/README.vm
and implemented by the 'ipmi-bmc-extern' model on the host side.
To use, start the Aspeed BMC machine with :
-chardev socket,id=ipmi0,host=localhost,port=9002,ipv4,server,nowait \
-global driver=aspeed.ibt,property=chardev,value=ipmi0
and the PowerNV machine with :
-chardev socket,id=ipmi0,host=localhost,port=9002,reconnect=10 \
-device ipmi-bmc-extern,id=bmc0,chardev=ipmi0 \
-device isa-ipmi-bt,bmc=bmc0,irq=10 -nodefaults
Cc: Hao Wu <wuhaotsh@google.com>
Cc: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
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| #
0084c026 |
| 27-Nov-2017 |
Cédric Le Goater <clg@kaod.org> |
hw/misc: Add basic Aspeed PWM model
Just enough to quiet down the output when running with the logs.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
|
| #
2e7de8b3 |
| 19-Jan-2023 |
Joel Stanley <joel@jms.id.au> |
hw/misc: Add basic Aspeed GFX model
Enough model to capture the pinmux writes to enable correct operation of
the parts of pinmux that depend on GFX registers.
Signed-off-by: Joel Stanley <joel@jms.
hw/misc: Add basic Aspeed GFX model
Enough model to capture the pinmux writes to enable correct operation of
the parts of pinmux that depend on GFX registers.
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|
| #
428cd2e9 |
| 18-Oct-2021 |
Cédric Le Goater <clg@kaod.org> |
aspeed/smc: Improve support for the alternate boot function
Map the WDT2 registers in the AST2600 FMC memory region by creating a
local address space on top of WDT2 memory region.
The model only im
aspeed/smc: Improve support for the alternate boot function
Map the WDT2 registers in the AST2600 FMC memory region by creating a
local address space on top of WDT2 memory region.
The model only implements the enable bit of the control register. The
reload register uses a 0.1s unit instead of a 1us. Values are
converted on the fly when doing the accesses. The restart register is
the same.
TODO: This needs a rework since the FMC WDT2 device is an independent
watchdog logic embedded in the FMC device.
Cc: Peter Delevoryas <pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
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| #
70bcd7e2 |
| 18-Oct-2021 |
Cédric Le Goater <clg@kaod.org> |
aspeed: Initialize the watchdog device models before the FMC models
Next changes will map the WDT2 registers in the AST2600 FMC memory
region. Make sure the MemoryRegion pointers are correctly initi
aspeed: Initialize the watchdog device models before the FMC models
Next changes will map the WDT2 registers in the AST2600 FMC memory
region. Make sure the MemoryRegion pointers are correctly initialized
before setting the object links.
Do the same in the Aspeed AST2400 and AST2500 SoC models for
consistency.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
show more ...
|
| #
ba142525 |
| 12-Nov-2024 |
Guenter Roeck <linux@roeck-us.net> |
aspeed: Add uhci support for ast2600
Add UHCI support for the ast2600 SoC. With this patch, UHCI support
is successfully enabled on the rainier-bmc and ast2600-evb machines.
Signed-off-by: Guenter
aspeed: Add uhci support for ast2600
Add UHCI support for the ast2600 SoC. With this patch, UHCI support
is successfully enabled on the rainier-bmc and ast2600-evb machines.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
show more ...
|
| #
9dada524 |
| 04-Dec-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers
Currently, it set the hardcode value of capability registers to all ASPEED SOCs
However, the value of capab
hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers
Currently, it set the hardcode value of capability registers to all ASPEED SOCs
However, the value of capability registers should be different for all ASPEED
SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for
64-bits System Bus support for AST2700.
Introduce a new "capareg" class member whose data type is uint_64 to set the
different Capability Registers to all ASPEED SOCs.
The value of Capability Register is "0x0000000001e80080" for AST2400 and
AST2500. The value of Capability Register is "0x0000000701f80080" for AST2600.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
show more ...
|
| #
4fee565e |
| 04-Dec-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/arm/aspeed: Fix coding style
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
|
| #
de042938 |
| 04-Dec-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers
Currently, it set the hardcode value of capability registers to all ASPEED SOCs
However, the value of capab
hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers
Currently, it set the hardcode value of capability registers to all ASPEED SOCs
However, the value of capability registers should be different for all ASPEED
SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for
64-bits System Bus support for AST2700.
Introduce a new "capareg" class member whose data type is uint_64 to set the
different Capability Registers to all ASPEED SOCs.
The value of Capability Register is "0x0000000001e80080" for AST2400 and
AST2500. The value of Capability Register is "0x0000000701f80080" for AST2600.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
show more ...
|
| #
5718439c |
| 04-Dec-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/arm/aspeed: Fix coding style
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
|
| #
8d40a557 |
| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L
168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge)
1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L
168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge)
1E6E:D200-1E6E:D3FF PCIe Host Controller (RC)
1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller
6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
| #
68857fbe |
| 07-Apr-2021 |
Cédric Le Goater <clg@kaod.org> |
hw/misc: Add an iBT device model
Implement an IPMI BT interface model using a chardev backend to
communicate with an external PowerNV machine. It uses the OpenIPMI
simulator protocol for virtual mac
hw/misc: Add an iBT device model
Implement an IPMI BT interface model using a chardev backend to
communicate with an external PowerNV machine. It uses the OpenIPMI
simulator protocol for virtual machines described in :
https://github.com/cminyard/openipmi/blob/master/lanserv/README.vm
and implemented by the 'ipmi-bmc-extern' model on the host side.
To use, start the Aspeed BMC machine with :
-chardev socket,id=ipmi0,host=localhost,port=9002,ipv4,server,nowait \
-global driver=aspeed.ibt,property=chardev,value=ipmi0
and the PowerNV machine with :
-chardev socket,id=ipmi0,host=localhost,port=9002,reconnect=10 \
-device ipmi-bmc-extern,id=bmc0,chardev=ipmi0 \
-device isa-ipmi-bt,bmc=bmc0,irq=10 -nodefaults
Cc: Hao Wu <wuhaotsh@google.com>
Cc: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
| #
a1bf0762 |
| 27-Nov-2017 |
Cédric Le Goater <clg@kaod.org> |
hw/misc: Add basic Aspeed PWM model
Just enough to quiet down the output when running with the logs.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
|
| #
a726d631 |
| 19-Jan-2023 |
Joel Stanley <joel@jms.id.au> |
hw/misc: Add basic Aspeed GFX model
Enough model to capture the pinmux writes to enable correct operation of
the parts of pinmux that depend on GFX registers.
Signed-off-by: Joel Stanley <joel@jms.
hw/misc: Add basic Aspeed GFX model
Enough model to capture the pinmux writes to enable correct operation of
the parts of pinmux that depend on GFX registers.
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|
| #
f1d73a0e |
| 18-Oct-2021 |
Cédric Le Goater <clg@kaod.org> |
aspeed/smc: Improve support for the alternate boot function
Map the WDT2 registers in the AST2600 FMC memory region by creating a
local address space on top of WDT2 memory region.
The model only im
aspeed/smc: Improve support for the alternate boot function
Map the WDT2 registers in the AST2600 FMC memory region by creating a
local address space on top of WDT2 memory region.
The model only implements the enable bit of the control register. The
reload register uses a 0.1s unit instead of a 1us. Values are
converted on the fly when doing the accesses. The restart register is
the same.
TODO: This needs a rework since the FMC WDT2 device is an independent
watchdog logic embedded in the FMC device.
Cc: Peter Delevoryas <pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|