1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/clock/aspeed-clock.h> 3 4/ { 5 model = "Aspeed BMC"; 6 compatible = "aspeed,ast2400"; 7 #address-cells = <1>; 8 #size-cells = <1>; 9 interrupt-parent = <&vic>; 10 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 i2c6 = &i2c6; 19 i2c7 = &i2c7; 20 i2c8 = &i2c8; 21 i2c9 = &i2c9; 22 i2c10 = &i2c10; 23 i2c11 = &i2c11; 24 i2c12 = &i2c12; 25 i2c13 = &i2c13; 26 serial0 = &uart1; 27 serial1 = &uart2; 28 serial2 = &uart3; 29 serial3 = &uart4; 30 serial4 = &uart5; 31 serial5 = &vuart; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu@0 { 39 compatible = "arm,arm926ej-s"; 40 device_type = "cpu"; 41 reg = <0>; 42 }; 43 }; 44 45 memory@40000000 { 46 device_type = "memory"; 47 reg = <0x40000000 0>; 48 }; 49 50 ahb { 51 compatible = "simple-bus"; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 ranges; 55 56 fmc: spi@1e620000 { 57 reg = <0x1e620000 0x94>, <0x20000000 0x10000000>; 58 #address-cells = <1>; 59 #size-cells = <0>; 60 compatible = "aspeed,ast2400-fmc"; 61 clocks = <&syscon ASPEED_CLK_AHB>; 62 status = "disabled"; 63 interrupts = <19>; 64 flash@0 { 65 reg = < 0 >; 66 compatible = "jedec,spi-nor"; 67 spi-rx-bus-width = <2>; 68 spi-max-frequency = <50000000>; 69 status = "disabled"; 70 }; 71 flash@1 { 72 reg = < 1 >; 73 compatible = "jedec,spi-nor"; 74 spi-rx-bus-width = <2>; 75 spi-max-frequency = <50000000>; 76 status = "disabled"; 77 }; 78 flash@2 { 79 reg = < 2 >; 80 compatible = "jedec,spi-nor"; 81 spi-rx-bus-width = <2>; 82 spi-max-frequency = <50000000>; 83 status = "disabled"; 84 }; 85 flash@3 { 86 reg = < 3 >; 87 compatible = "jedec,spi-nor"; 88 spi-rx-bus-width = <2>; 89 spi-max-frequency = <50000000>; 90 status = "disabled"; 91 }; 92 flash@4 { 93 reg = < 4 >; 94 compatible = "jedec,spi-nor"; 95 spi-rx-bus-width = <2>; 96 spi-max-frequency = <50000000>; 97 status = "disabled"; 98 }; 99 }; 100 101 spi: spi@1e630000 { 102 reg = <0x1e630000 0x18>, <0x30000000 0x10000000>; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 compatible = "aspeed,ast2400-spi"; 106 clocks = <&syscon ASPEED_CLK_AHB>; 107 status = "disabled"; 108 flash@0 { 109 reg = < 0 >; 110 compatible = "jedec,spi-nor"; 111 spi-max-frequency = <50000000>; 112 spi-rx-bus-width = <2>; 113 status = "disabled"; 114 }; 115 }; 116 117 vic: interrupt-controller@1e6c0080 { 118 compatible = "aspeed,ast2400-vic"; 119 interrupt-controller; 120 #interrupt-cells = <1>; 121 valid-sources = <0xffffffff 0x0007ffff>; 122 reg = <0x1e6c0080 0x80>; 123 }; 124 125 cvic: interrupt-controller@1e6c2000 { 126 compatible = "aspeed,ast2400-cvic", "aspeed,cvic"; 127 valid-sources = <0x7fffffff>; 128 reg = <0x1e6c2000 0x80>; 129 }; 130 131 mac0: ethernet@1e660000 { 132 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; 133 reg = <0x1e660000 0x180>; 134 interrupts = <2>; 135 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; 136 status = "disabled"; 137 }; 138 139 mac1: ethernet@1e680000 { 140 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; 141 reg = <0x1e680000 0x180>; 142 interrupts = <3>; 143 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; 144 status = "disabled"; 145 }; 146 147 ehci0: usb@1e6a1000 { 148 compatible = "aspeed,ast2400-ehci", "generic-ehci"; 149 reg = <0x1e6a1000 0x100>; 150 interrupts = <5>; 151 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_usb2h_default>; 154 status = "disabled"; 155 }; 156 157 uhci: usb@1e6b0000 { 158 compatible = "aspeed,ast2400-uhci", "generic-uhci"; 159 reg = <0x1e6b0000 0x100>; 160 interrupts = <14>; 161 #ports = <3>; 162 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; 163 status = "disabled"; 164 /* 165 * No default pinmux, it will follow EHCI, use an explicit pinmux 166 * override if you don't enable EHCI 167 */ 168 }; 169 170 vhub: usb-vhub@1e6a0000 { 171 compatible = "aspeed,ast2400-usb-vhub"; 172 reg = <0x1e6a0000 0x300>; 173 interrupts = <5>; 174 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 175 aspeed,vhub-downstream-ports = <5>; 176 aspeed,vhub-generic-endpoints = <15>; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_usb2d_default>; 179 status = "disabled"; 180 }; 181 182 apb@1e6e0000 { 183 compatible = "simple-bus"; 184 reg = <0x1e6e0000 0x00010000>; 185 #address-cells = <1>; 186 #size-cells = <1>; 187 ranges; 188 189 syscon: syscon@1e6e2000 { 190 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; 191 reg = <0x1e6e2000 0x1a8>; 192 #address-cells = <1>; 193 #size-cells = <1>; 194 ranges = <0 0x1e6e2000 0x1000>; 195 #clock-cells = <1>; 196 #reset-cells = <1>; 197 198 p2a: p2a-control@2c { 199 reg = <0x2c 0x4>; 200 compatible = "aspeed,ast2400-p2a-ctrl"; 201 status = "disabled"; 202 }; 203 204 silicon-id@7c { 205 compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id"; 206 reg = <0x7c 0x4>; 207 }; 208 209 pinctrl: pinctrl@80 { 210 reg = <0x80 0x18>, <0xa0 0x10>; 211 compatible = "aspeed,ast2400-pinctrl"; 212 }; 213 }; 214 215 rng: hwrng@1e6e2078 { 216 compatible = "timeriomem_rng"; 217 reg = <0x1e6e2078 0x4>; 218 period = <1>; 219 quality = <100>; 220 }; 221 222 adc: adc@1e6e9000 { 223 compatible = "aspeed,ast2400-adc"; 224 reg = <0x1e6e9000 0xb0>; 225 clocks = <&syscon ASPEED_CLK_APB>; 226 resets = <&syscon ASPEED_RESET_ADC>; 227 #io-channel-cells = <1>; 228 status = "disabled"; 229 }; 230 }; 231 232 /* There's another APB mapping at 0x1e6f0000 for 0x00010000 */ 233 234 sram: sram@1e720000 { 235 compatible = "mmio-sram"; 236 reg = <0x1e720000 0x8000>; // 32K 237 ranges; 238 #address-cells = <1>; 239 #size-cells = <1>; 240 }; 241 242 video: video@1e700000 { 243 compatible = "aspeed,ast2400-video-engine"; 244 reg = <0x1e700000 0x1000>; 245 clocks = <&syscon ASPEED_CLK_GATE_VCLK>, 246 <&syscon ASPEED_CLK_GATE_ECLK>; 247 clock-names = "vclk", "eclk"; 248 interrupts = <7>; 249 status = "disabled"; 250 }; 251 252 sdmmc: sd-controller@1e740000 { 253 compatible = "aspeed,ast2400-sd-controller"; 254 reg = <0x1e740000 0x100>; 255 #address-cells = <1>; 256 #size-cells = <1>; 257 ranges = <0 0x1e740000 0x10000>; 258 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; 259 status = "disabled"; 260 261 sdhci0: sdhci@100 { 262 compatible = "aspeed,ast2400-sdhci"; 263 reg = <0x100 0x100>; 264 interrupts = <26>; 265 sdhci,auto-cmd12; 266 clocks = <&syscon ASPEED_CLK_SDIO>; 267 status = "disabled"; 268 }; 269 270 sdhci1: sdhci@200 { 271 compatible = "aspeed,ast2400-sdhci"; 272 reg = <0x200 0x100>; 273 interrupts = <26>; 274 sdhci,auto-cmd12; 275 clocks = <&syscon ASPEED_CLK_SDIO>; 276 status = "disabled"; 277 }; 278 }; 279 280 apb@1e780000 { 281 compatible = "simple-bus"; 282 reg = <0x1e780000 0x00010000>; 283 #address-cells = <1>; 284 #size-cells = <1>; 285 ranges; 286 287 gpio: gpio@1e780000 { 288 #gpio-cells = <2>; 289 gpio-controller; 290 compatible = "aspeed,ast2400-gpio"; 291 reg = <0x1e780000 0x1000>; 292 interrupts = <20>; 293 gpio-ranges = <&pinctrl 0 0 220>; 294 clocks = <&syscon ASPEED_CLK_APB>; 295 interrupt-controller; 296 #interrupt-cells = <2>; 297 }; 298 299 timer: timer@1e782000 { 300 /* This timer is a Faraday FTTMR010 derivative */ 301 compatible = "aspeed,ast2400-timer"; 302 reg = <0x1e782000 0x90>; 303 interrupts = <16 17 18 35 36 37 38 39>; 304 clocks = <&syscon ASPEED_CLK_APB>; 305 clock-names = "PCLK"; 306 }; 307 308 rtc: rtc@1e781000 { 309 compatible = "aspeed,ast2400-rtc"; 310 reg = <0x1e781000 0x18>; 311 status = "disabled"; 312 }; 313 314 uart1: serial@1e783000 { 315 compatible = "ns16550a"; 316 reg = <0x1e783000 0x20>; 317 reg-shift = <2>; 318 interrupts = <9>; 319 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; 320 resets = <&lpc_reset 4>; 321 no-loopback-test; 322 status = "disabled"; 323 }; 324 325 uart5: serial@1e784000 { 326 compatible = "ns16550a"; 327 reg = <0x1e784000 0x20>; 328 reg-shift = <2>; 329 interrupts = <10>; 330 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; 331 no-loopback-test; 332 status = "disabled"; 333 }; 334 335 wdt1: watchdog@1e785000 { 336 compatible = "aspeed,ast2400-wdt"; 337 reg = <0x1e785000 0x1c>; 338 clocks = <&syscon ASPEED_CLK_APB>; 339 }; 340 341 wdt2: watchdog@1e785020 { 342 compatible = "aspeed,ast2400-wdt"; 343 reg = <0x1e785020 0x1c>; 344 clocks = <&syscon ASPEED_CLK_APB>; 345 }; 346 347 pwm_tacho: pwm-tacho-controller@1e786000 { 348 compatible = "aspeed,ast2400-pwm-tacho"; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 reg = <0x1e786000 0x1000>; 352 clocks = <&syscon ASPEED_CLK_24M>; 353 resets = <&syscon ASPEED_RESET_PWM>; 354 status = "disabled"; 355 }; 356 357 vuart: serial@1e787000 { 358 compatible = "aspeed,ast2400-vuart"; 359 reg = <0x1e787000 0x40>; 360 reg-shift = <2>; 361 interrupts = <8>; 362 clocks = <&syscon ASPEED_CLK_APB>; 363 no-loopback-test; 364 status = "disabled"; 365 }; 366 367 lpc: lpc@1e789000 { 368 compatible = "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"; 369 reg = <0x1e789000 0x1000>; 370 reg-io-width = <4>; 371 372 #address-cells = <1>; 373 #size-cells = <1>; 374 ranges = <0x0 0x1e789000 0x1000>; 375 376 lpc_ctrl: lpc-ctrl@80 { 377 compatible = "aspeed,ast2400-lpc-ctrl"; 378 reg = <0x80 0x10>; 379 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 380 status = "disabled"; 381 }; 382 383 lpc_snoop: lpc-snoop@90 { 384 compatible = "aspeed,ast2400-lpc-snoop"; 385 reg = <0x90 0x8>; 386 interrupts = <8>; 387 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 388 status = "disabled"; 389 }; 390 391 lhc: lhc@a0 { 392 compatible = "aspeed,ast2400-lhc"; 393 reg = <0xa0 0x24 0xc8 0x8>; 394 }; 395 396 lpc_reset: reset-controller@98 { 397 compatible = "aspeed,ast2400-lpc-reset"; 398 reg = <0x98 0x4>; 399 #reset-cells = <1>; 400 }; 401 402 ibt: ibt@140 { 403 compatible = "aspeed,ast2400-ibt-bmc"; 404 reg = <0x140 0x18>; 405 interrupts = <8>; 406 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 407 status = "disabled"; 408 }; 409 410 uart_routing: uart-routing@9c { 411 compatible = "aspeed,ast2400-uart-routing"; 412 reg = <0x9c 0x4>; 413 status = "disabled"; 414 }; 415 }; 416 417 peci0: peci-controller@1e78b000 { 418 compatible = "aspeed,ast2400-peci"; 419 reg = <0x1e78b000 0x60>; 420 interrupts = <15>; 421 clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; 422 resets = <&syscon ASPEED_RESET_PECI>; 423 cmd-timeout-ms = <1000>; 424 clock-frequency = <1000000>; 425 status = "disabled"; 426 }; 427 428 uart2: serial@1e78d000 { 429 compatible = "ns16550a"; 430 reg = <0x1e78d000 0x20>; 431 reg-shift = <2>; 432 interrupts = <32>; 433 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; 434 resets = <&lpc_reset 5>; 435 no-loopback-test; 436 status = "disabled"; 437 }; 438 439 uart3: serial@1e78e000 { 440 compatible = "ns16550a"; 441 reg = <0x1e78e000 0x20>; 442 reg-shift = <2>; 443 interrupts = <33>; 444 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; 445 resets = <&lpc_reset 6>; 446 no-loopback-test; 447 status = "disabled"; 448 }; 449 450 uart4: serial@1e78f000 { 451 compatible = "ns16550a"; 452 reg = <0x1e78f000 0x20>; 453 reg-shift = <2>; 454 interrupts = <34>; 455 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; 456 resets = <&lpc_reset 7>; 457 no-loopback-test; 458 status = "disabled"; 459 }; 460 461 i2c: bus@1e78a000 { 462 compatible = "simple-bus"; 463 #address-cells = <1>; 464 #size-cells = <1>; 465 ranges = <0 0x1e78a000 0x1000>; 466 }; 467 }; 468 469 /* There's another APB mapping at 0x1e790000 for 0x00010000 */ 470 }; 471}; 472 473&i2c { 474 i2c_ic: interrupt-controller@0 { 475 #interrupt-cells = <1>; 476 compatible = "aspeed,ast2400-i2c-ic"; 477 reg = <0x0 0x40>; 478 interrupts = <12>; 479 interrupt-controller; 480 }; 481 482 i2c0: i2c@40 { 483 #address-cells = <1>; 484 #size-cells = <0>; 485 486 reg = <0x40 0x40>; 487 compatible = "aspeed,ast2400-i2c-bus"; 488 clocks = <&syscon ASPEED_CLK_APB>; 489 resets = <&syscon ASPEED_RESET_I2C>; 490 bus-frequency = <100000>; 491 interrupts = <0>; 492 interrupt-parent = <&i2c_ic>; 493 status = "disabled"; 494 /* Does not need pinctrl properties */ 495 }; 496 497 i2c1: i2c@80 { 498 #address-cells = <1>; 499 #size-cells = <0>; 500 501 reg = <0x80 0x40>; 502 compatible = "aspeed,ast2400-i2c-bus"; 503 clocks = <&syscon ASPEED_CLK_APB>; 504 resets = <&syscon ASPEED_RESET_I2C>; 505 bus-frequency = <100000>; 506 interrupts = <1>; 507 interrupt-parent = <&i2c_ic>; 508 status = "disabled"; 509 /* Does not need pinctrl properties */ 510 }; 511 512 i2c2: i2c@c0 { 513 #address-cells = <1>; 514 #size-cells = <0>; 515 516 reg = <0xc0 0x40>; 517 compatible = "aspeed,ast2400-i2c-bus"; 518 clocks = <&syscon ASPEED_CLK_APB>; 519 resets = <&syscon ASPEED_RESET_I2C>; 520 bus-frequency = <100000>; 521 interrupts = <2>; 522 interrupt-parent = <&i2c_ic>; 523 pinctrl-names = "default"; 524 pinctrl-0 = <&pinctrl_i2c3_default>; 525 status = "disabled"; 526 }; 527 528 i2c3: i2c@100 { 529 #address-cells = <1>; 530 #size-cells = <0>; 531 532 reg = <0x100 0x40>; 533 compatible = "aspeed,ast2400-i2c-bus"; 534 clocks = <&syscon ASPEED_CLK_APB>; 535 resets = <&syscon ASPEED_RESET_I2C>; 536 bus-frequency = <100000>; 537 interrupts = <3>; 538 interrupt-parent = <&i2c_ic>; 539 pinctrl-names = "default"; 540 pinctrl-0 = <&pinctrl_i2c4_default>; 541 status = "disabled"; 542 }; 543 544 i2c4: i2c@140 { 545 #address-cells = <1>; 546 #size-cells = <0>; 547 548 reg = <0x140 0x40>; 549 compatible = "aspeed,ast2400-i2c-bus"; 550 clocks = <&syscon ASPEED_CLK_APB>; 551 resets = <&syscon ASPEED_RESET_I2C>; 552 bus-frequency = <100000>; 553 interrupts = <4>; 554 interrupt-parent = <&i2c_ic>; 555 pinctrl-names = "default"; 556 pinctrl-0 = <&pinctrl_i2c5_default>; 557 status = "disabled"; 558 }; 559 560 i2c5: i2c@180 { 561 #address-cells = <1>; 562 #size-cells = <0>; 563 564 reg = <0x180 0x40>; 565 compatible = "aspeed,ast2400-i2c-bus"; 566 clocks = <&syscon ASPEED_CLK_APB>; 567 resets = <&syscon ASPEED_RESET_I2C>; 568 bus-frequency = <100000>; 569 interrupts = <5>; 570 interrupt-parent = <&i2c_ic>; 571 pinctrl-names = "default"; 572 pinctrl-0 = <&pinctrl_i2c6_default>; 573 status = "disabled"; 574 }; 575 576 i2c6: i2c@1c0 { 577 #address-cells = <1>; 578 #size-cells = <0>; 579 580 reg = <0x1c0 0x40>; 581 compatible = "aspeed,ast2400-i2c-bus"; 582 clocks = <&syscon ASPEED_CLK_APB>; 583 resets = <&syscon ASPEED_RESET_I2C>; 584 bus-frequency = <100000>; 585 interrupts = <6>; 586 interrupt-parent = <&i2c_ic>; 587 pinctrl-names = "default"; 588 pinctrl-0 = <&pinctrl_i2c7_default>; 589 status = "disabled"; 590 }; 591 592 i2c7: i2c@300 { 593 #address-cells = <1>; 594 #size-cells = <0>; 595 596 reg = <0x300 0x40>; 597 compatible = "aspeed,ast2400-i2c-bus"; 598 clocks = <&syscon ASPEED_CLK_APB>; 599 resets = <&syscon ASPEED_RESET_I2C>; 600 bus-frequency = <100000>; 601 interrupts = <7>; 602 interrupt-parent = <&i2c_ic>; 603 pinctrl-names = "default"; 604 pinctrl-0 = <&pinctrl_i2c8_default>; 605 status = "disabled"; 606 }; 607 608 i2c8: i2c@340 { 609 #address-cells = <1>; 610 #size-cells = <0>; 611 612 reg = <0x340 0x40>; 613 compatible = "aspeed,ast2400-i2c-bus"; 614 clocks = <&syscon ASPEED_CLK_APB>; 615 resets = <&syscon ASPEED_RESET_I2C>; 616 bus-frequency = <100000>; 617 interrupts = <8>; 618 interrupt-parent = <&i2c_ic>; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&pinctrl_i2c9_default>; 621 status = "disabled"; 622 }; 623 624 i2c9: i2c@380 { 625 #address-cells = <1>; 626 #size-cells = <0>; 627 628 reg = <0x380 0x40>; 629 compatible = "aspeed,ast2400-i2c-bus"; 630 clocks = <&syscon ASPEED_CLK_APB>; 631 resets = <&syscon ASPEED_RESET_I2C>; 632 bus-frequency = <100000>; 633 interrupts = <9>; 634 interrupt-parent = <&i2c_ic>; 635 pinctrl-names = "default"; 636 pinctrl-0 = <&pinctrl_i2c10_default>; 637 status = "disabled"; 638 }; 639 640 i2c10: i2c@3c0 { 641 #address-cells = <1>; 642 #size-cells = <0>; 643 644 reg = <0x3c0 0x40>; 645 compatible = "aspeed,ast2400-i2c-bus"; 646 clocks = <&syscon ASPEED_CLK_APB>; 647 resets = <&syscon ASPEED_RESET_I2C>; 648 bus-frequency = <100000>; 649 interrupts = <10>; 650 interrupt-parent = <&i2c_ic>; 651 pinctrl-names = "default"; 652 pinctrl-0 = <&pinctrl_i2c11_default>; 653 status = "disabled"; 654 }; 655 656 i2c11: i2c@400 { 657 #address-cells = <1>; 658 #size-cells = <0>; 659 660 reg = <0x400 0x40>; 661 compatible = "aspeed,ast2400-i2c-bus"; 662 clocks = <&syscon ASPEED_CLK_APB>; 663 resets = <&syscon ASPEED_RESET_I2C>; 664 bus-frequency = <100000>; 665 interrupts = <11>; 666 interrupt-parent = <&i2c_ic>; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&pinctrl_i2c12_default>; 669 status = "disabled"; 670 }; 671 672 i2c12: i2c@440 { 673 #address-cells = <1>; 674 #size-cells = <0>; 675 676 reg = <0x440 0x40>; 677 compatible = "aspeed,ast2400-i2c-bus"; 678 clocks = <&syscon ASPEED_CLK_APB>; 679 resets = <&syscon ASPEED_RESET_I2C>; 680 bus-frequency = <100000>; 681 interrupts = <12>; 682 interrupt-parent = <&i2c_ic>; 683 pinctrl-names = "default"; 684 pinctrl-0 = <&pinctrl_i2c13_default>; 685 status = "disabled"; 686 }; 687 688 i2c13: i2c@480 { 689 #address-cells = <1>; 690 #size-cells = <0>; 691 692 reg = <0x480 0x40>; 693 compatible = "aspeed,ast2400-i2c-bus"; 694 clocks = <&syscon ASPEED_CLK_APB>; 695 resets = <&syscon ASPEED_RESET_I2C>; 696 bus-frequency = <100000>; 697 interrupts = <13>; 698 interrupt-parent = <&i2c_ic>; 699 pinctrl-names = "default"; 700 pinctrl-0 = <&pinctrl_i2c14_default>; 701 status = "disabled"; 702 }; 703}; 704 705&pinctrl { 706 pinctrl_acpi_default: acpi_default { 707 function = "ACPI"; 708 groups = "ACPI"; 709 }; 710 711 pinctrl_adc0_default: adc0_default { 712 function = "ADC0"; 713 groups = "ADC0"; 714 }; 715 716 pinctrl_adc1_default: adc1_default { 717 function = "ADC1"; 718 groups = "ADC1"; 719 }; 720 721 pinctrl_adc10_default: adc10_default { 722 function = "ADC10"; 723 groups = "ADC10"; 724 }; 725 726 pinctrl_adc11_default: adc11_default { 727 function = "ADC11"; 728 groups = "ADC11"; 729 }; 730 731 pinctrl_adc12_default: adc12_default { 732 function = "ADC12"; 733 groups = "ADC12"; 734 }; 735 736 pinctrl_adc13_default: adc13_default { 737 function = "ADC13"; 738 groups = "ADC13"; 739 }; 740 741 pinctrl_adc14_default: adc14_default { 742 function = "ADC14"; 743 groups = "ADC14"; 744 }; 745 746 pinctrl_adc15_default: adc15_default { 747 function = "ADC15"; 748 groups = "ADC15"; 749 }; 750 751 pinctrl_adc2_default: adc2_default { 752 function = "ADC2"; 753 groups = "ADC2"; 754 }; 755 756 pinctrl_adc3_default: adc3_default { 757 function = "ADC3"; 758 groups = "ADC3"; 759 }; 760 761 pinctrl_adc4_default: adc4_default { 762 function = "ADC4"; 763 groups = "ADC4"; 764 }; 765 766 pinctrl_adc5_default: adc5_default { 767 function = "ADC5"; 768 groups = "ADC5"; 769 }; 770 771 pinctrl_adc6_default: adc6_default { 772 function = "ADC6"; 773 groups = "ADC6"; 774 }; 775 776 pinctrl_adc7_default: adc7_default { 777 function = "ADC7"; 778 groups = "ADC7"; 779 }; 780 781 pinctrl_adc8_default: adc8_default { 782 function = "ADC8"; 783 groups = "ADC8"; 784 }; 785 786 pinctrl_adc9_default: adc9_default { 787 function = "ADC9"; 788 groups = "ADC9"; 789 }; 790 791 pinctrl_bmcint_default: bmcint_default { 792 function = "BMCINT"; 793 groups = "BMCINT"; 794 }; 795 796 pinctrl_ddcclk_default: ddcclk_default { 797 function = "DDCCLK"; 798 groups = "DDCCLK"; 799 }; 800 801 pinctrl_ddcdat_default: ddcdat_default { 802 function = "DDCDAT"; 803 groups = "DDCDAT"; 804 }; 805 806 pinctrl_extrst_default: extrst_default { 807 function = "EXTRST"; 808 groups = "EXTRST"; 809 }; 810 811 pinctrl_flack_default: flack_default { 812 function = "FLACK"; 813 groups = "FLACK"; 814 }; 815 816 pinctrl_flbusy_default: flbusy_default { 817 function = "FLBUSY"; 818 groups = "FLBUSY"; 819 }; 820 821 pinctrl_flwp_default: flwp_default { 822 function = "FLWP"; 823 groups = "FLWP"; 824 }; 825 826 pinctrl_gpid_default: gpid_default { 827 function = "GPID"; 828 groups = "GPID"; 829 }; 830 831 pinctrl_gpid0_default: gpid0_default { 832 function = "GPID0"; 833 groups = "GPID0"; 834 }; 835 836 pinctrl_gpid2_default: gpid2_default { 837 function = "GPID2"; 838 groups = "GPID2"; 839 }; 840 841 pinctrl_gpid4_default: gpid4_default { 842 function = "GPID4"; 843 groups = "GPID4"; 844 }; 845 846 pinctrl_gpid6_default: gpid6_default { 847 function = "GPID6"; 848 groups = "GPID6"; 849 }; 850 851 pinctrl_gpie0_default: gpie0_default { 852 function = "GPIE0"; 853 groups = "GPIE0"; 854 }; 855 856 pinctrl_gpie2_default: gpie2_default { 857 function = "GPIE2"; 858 groups = "GPIE2"; 859 }; 860 861 pinctrl_gpie4_default: gpie4_default { 862 function = "GPIE4"; 863 groups = "GPIE4"; 864 }; 865 866 pinctrl_gpie6_default: gpie6_default { 867 function = "GPIE6"; 868 groups = "GPIE6"; 869 }; 870 871 pinctrl_i2c10_default: i2c10_default { 872 function = "I2C10"; 873 groups = "I2C10"; 874 }; 875 876 pinctrl_i2c11_default: i2c11_default { 877 function = "I2C11"; 878 groups = "I2C11"; 879 }; 880 881 pinctrl_i2c12_default: i2c12_default { 882 function = "I2C12"; 883 groups = "I2C12"; 884 }; 885 886 pinctrl_i2c13_default: i2c13_default { 887 function = "I2C13"; 888 groups = "I2C13"; 889 }; 890 891 pinctrl_i2c14_default: i2c14_default { 892 function = "I2C14"; 893 groups = "I2C14"; 894 }; 895 896 pinctrl_i2c3_default: i2c3_default { 897 function = "I2C3"; 898 groups = "I2C3"; 899 }; 900 901 pinctrl_i2c4_default: i2c4_default { 902 function = "I2C4"; 903 groups = "I2C4"; 904 }; 905 906 pinctrl_i2c5_default: i2c5_default { 907 function = "I2C5"; 908 groups = "I2C5"; 909 }; 910 911 pinctrl_i2c6_default: i2c6_default { 912 function = "I2C6"; 913 groups = "I2C6"; 914 }; 915 916 pinctrl_i2c7_default: i2c7_default { 917 function = "I2C7"; 918 groups = "I2C7"; 919 }; 920 921 pinctrl_i2c8_default: i2c8_default { 922 function = "I2C8"; 923 groups = "I2C8"; 924 }; 925 926 pinctrl_i2c9_default: i2c9_default { 927 function = "I2C9"; 928 groups = "I2C9"; 929 }; 930 931 pinctrl_lpcpd_default: lpcpd_default { 932 function = "LPCPD"; 933 groups = "LPCPD"; 934 }; 935 936 pinctrl_lpcpme_default: lpcpme_default { 937 function = "LPCPME"; 938 groups = "LPCPME"; 939 }; 940 941 pinctrl_lpcrst_default: lpcrst_default { 942 function = "LPCRST"; 943 groups = "LPCRST"; 944 }; 945 946 pinctrl_lpcsmi_default: lpcsmi_default { 947 function = "LPCSMI"; 948 groups = "LPCSMI"; 949 }; 950 951 pinctrl_mac1link_default: mac1link_default { 952 function = "MAC1LINK"; 953 groups = "MAC1LINK"; 954 }; 955 956 pinctrl_mac2link_default: mac2link_default { 957 function = "MAC2LINK"; 958 groups = "MAC2LINK"; 959 }; 960 961 pinctrl_mdio1_default: mdio1_default { 962 function = "MDIO1"; 963 groups = "MDIO1"; 964 }; 965 966 pinctrl_mdio2_default: mdio2_default { 967 function = "MDIO2"; 968 groups = "MDIO2"; 969 }; 970 971 pinctrl_ncts1_default: ncts1_default { 972 function = "NCTS1"; 973 groups = "NCTS1"; 974 }; 975 976 pinctrl_ncts2_default: ncts2_default { 977 function = "NCTS2"; 978 groups = "NCTS2"; 979 }; 980 981 pinctrl_ncts3_default: ncts3_default { 982 function = "NCTS3"; 983 groups = "NCTS3"; 984 }; 985 986 pinctrl_ncts4_default: ncts4_default { 987 function = "NCTS4"; 988 groups = "NCTS4"; 989 }; 990 991 pinctrl_ndcd1_default: ndcd1_default { 992 function = "NDCD1"; 993 groups = "NDCD1"; 994 }; 995 996 pinctrl_ndcd2_default: ndcd2_default { 997 function = "NDCD2"; 998 groups = "NDCD2"; 999 }; 1000 1001 pinctrl_ndcd3_default: ndcd3_default { 1002 function = "NDCD3"; 1003 groups = "NDCD3"; 1004 }; 1005 1006 pinctrl_ndcd4_default: ndcd4_default { 1007 function = "NDCD4"; 1008 groups = "NDCD4"; 1009 }; 1010 1011 pinctrl_ndsr1_default: ndsr1_default { 1012 function = "NDSR1"; 1013 groups = "NDSR1"; 1014 }; 1015 1016 pinctrl_ndsr2_default: ndsr2_default { 1017 function = "NDSR2"; 1018 groups = "NDSR2"; 1019 }; 1020 1021 pinctrl_ndsr3_default: ndsr3_default { 1022 function = "NDSR3"; 1023 groups = "NDSR3"; 1024 }; 1025 1026 pinctrl_ndsr4_default: ndsr4_default { 1027 function = "NDSR4"; 1028 groups = "NDSR4"; 1029 }; 1030 1031 pinctrl_ndtr1_default: ndtr1_default { 1032 function = "NDTR1"; 1033 groups = "NDTR1"; 1034 }; 1035 1036 pinctrl_ndtr2_default: ndtr2_default { 1037 function = "NDTR2"; 1038 groups = "NDTR2"; 1039 }; 1040 1041 pinctrl_ndtr3_default: ndtr3_default { 1042 function = "NDTR3"; 1043 groups = "NDTR3"; 1044 }; 1045 1046 pinctrl_ndtr4_default: ndtr4_default { 1047 function = "NDTR4"; 1048 groups = "NDTR4"; 1049 }; 1050 1051 pinctrl_ndts4_default: ndts4_default { 1052 function = "NDTS4"; 1053 groups = "NDTS4"; 1054 }; 1055 1056 pinctrl_nri1_default: nri1_default { 1057 function = "NRI1"; 1058 groups = "NRI1"; 1059 }; 1060 1061 pinctrl_nri2_default: nri2_default { 1062 function = "NRI2"; 1063 groups = "NRI2"; 1064 }; 1065 1066 pinctrl_nri3_default: nri3_default { 1067 function = "NRI3"; 1068 groups = "NRI3"; 1069 }; 1070 1071 pinctrl_nri4_default: nri4_default { 1072 function = "NRI4"; 1073 groups = "NRI4"; 1074 }; 1075 1076 pinctrl_nrts1_default: nrts1_default { 1077 function = "NRTS1"; 1078 groups = "NRTS1"; 1079 }; 1080 1081 pinctrl_nrts2_default: nrts2_default { 1082 function = "NRTS2"; 1083 groups = "NRTS2"; 1084 }; 1085 1086 pinctrl_nrts3_default: nrts3_default { 1087 function = "NRTS3"; 1088 groups = "NRTS3"; 1089 }; 1090 1091 pinctrl_oscclk_default: oscclk_default { 1092 function = "OSCCLK"; 1093 groups = "OSCCLK"; 1094 }; 1095 1096 pinctrl_pwm0_default: pwm0_default { 1097 function = "PWM0"; 1098 groups = "PWM0"; 1099 }; 1100 1101 pinctrl_pwm1_default: pwm1_default { 1102 function = "PWM1"; 1103 groups = "PWM1"; 1104 }; 1105 1106 pinctrl_pwm2_default: pwm2_default { 1107 function = "PWM2"; 1108 groups = "PWM2"; 1109 }; 1110 1111 pinctrl_pwm3_default: pwm3_default { 1112 function = "PWM3"; 1113 groups = "PWM3"; 1114 }; 1115 1116 pinctrl_pwm4_default: pwm4_default { 1117 function = "PWM4"; 1118 groups = "PWM4"; 1119 }; 1120 1121 pinctrl_pwm5_default: pwm5_default { 1122 function = "PWM5"; 1123 groups = "PWM5"; 1124 }; 1125 1126 pinctrl_pwm6_default: pwm6_default { 1127 function = "PWM6"; 1128 groups = "PWM6"; 1129 }; 1130 1131 pinctrl_pwm7_default: pwm7_default { 1132 function = "PWM7"; 1133 groups = "PWM7"; 1134 }; 1135 1136 pinctrl_rgmii1_default: rgmii1_default { 1137 function = "RGMII1"; 1138 groups = "RGMII1"; 1139 }; 1140 1141 pinctrl_rgmii2_default: rgmii2_default { 1142 function = "RGMII2"; 1143 groups = "RGMII2"; 1144 }; 1145 1146 pinctrl_rmii1_default: rmii1_default { 1147 function = "RMII1"; 1148 groups = "RMII1"; 1149 }; 1150 1151 pinctrl_rmii2_default: rmii2_default { 1152 function = "RMII2"; 1153 groups = "RMII2"; 1154 }; 1155 1156 pinctrl_rom16_default: rom16_default { 1157 function = "ROM16"; 1158 groups = "ROM16"; 1159 }; 1160 1161 pinctrl_rom8_default: rom8_default { 1162 function = "ROM8"; 1163 groups = "ROM8"; 1164 }; 1165 1166 pinctrl_romcs1_default: romcs1_default { 1167 function = "ROMCS1"; 1168 groups = "ROMCS1"; 1169 }; 1170 1171 pinctrl_romcs2_default: romcs2_default { 1172 function = "ROMCS2"; 1173 groups = "ROMCS2"; 1174 }; 1175 1176 pinctrl_romcs3_default: romcs3_default { 1177 function = "ROMCS3"; 1178 groups = "ROMCS3"; 1179 }; 1180 1181 pinctrl_romcs4_default: romcs4_default { 1182 function = "ROMCS4"; 1183 groups = "ROMCS4"; 1184 }; 1185 1186 pinctrl_rxd1_default: rxd1_default { 1187 function = "RXD1"; 1188 groups = "RXD1"; 1189 }; 1190 1191 pinctrl_rxd2_default: rxd2_default { 1192 function = "RXD2"; 1193 groups = "RXD2"; 1194 }; 1195 1196 pinctrl_rxd3_default: rxd3_default { 1197 function = "RXD3"; 1198 groups = "RXD3"; 1199 }; 1200 1201 pinctrl_rxd4_default: rxd4_default { 1202 function = "RXD4"; 1203 groups = "RXD4"; 1204 }; 1205 1206 pinctrl_salt1_default: salt1_default { 1207 function = "SALT1"; 1208 groups = "SALT1"; 1209 }; 1210 1211 pinctrl_salt2_default: salt2_default { 1212 function = "SALT2"; 1213 groups = "SALT2"; 1214 }; 1215 1216 pinctrl_salt3_default: salt3_default { 1217 function = "SALT3"; 1218 groups = "SALT3"; 1219 }; 1220 1221 pinctrl_salt4_default: salt4_default { 1222 function = "SALT4"; 1223 groups = "SALT4"; 1224 }; 1225 1226 pinctrl_sd1_default: sd1_default { 1227 function = "SD1"; 1228 groups = "SD1"; 1229 }; 1230 1231 pinctrl_sd2_default: sd2_default { 1232 function = "SD2"; 1233 groups = "SD2"; 1234 }; 1235 1236 pinctrl_sgpmck_default: sgpmck_default { 1237 function = "SGPMCK"; 1238 groups = "SGPMCK"; 1239 }; 1240 1241 pinctrl_sgpmi_default: sgpmi_default { 1242 function = "SGPMI"; 1243 groups = "SGPMI"; 1244 }; 1245 1246 pinctrl_sgpmld_default: sgpmld_default { 1247 function = "SGPMLD"; 1248 groups = "SGPMLD"; 1249 }; 1250 1251 pinctrl_sgpmo_default: sgpmo_default { 1252 function = "SGPMO"; 1253 groups = "SGPMO"; 1254 }; 1255 1256 pinctrl_sgpsck_default: sgpsck_default { 1257 function = "SGPSCK"; 1258 groups = "SGPSCK"; 1259 }; 1260 1261 pinctrl_sgpsi0_default: sgpsi0_default { 1262 function = "SGPSI0"; 1263 groups = "SGPSI0"; 1264 }; 1265 1266 pinctrl_sgpsi1_default: sgpsi1_default { 1267 function = "SGPSI1"; 1268 groups = "SGPSI1"; 1269 }; 1270 1271 pinctrl_sgpsld_default: sgpsld_default { 1272 function = "SGPSLD"; 1273 groups = "SGPSLD"; 1274 }; 1275 1276 pinctrl_sioonctrl_default: sioonctrl_default { 1277 function = "SIOONCTRL"; 1278 groups = "SIOONCTRL"; 1279 }; 1280 1281 pinctrl_siopbi_default: siopbi_default { 1282 function = "SIOPBI"; 1283 groups = "SIOPBI"; 1284 }; 1285 1286 pinctrl_siopbo_default: siopbo_default { 1287 function = "SIOPBO"; 1288 groups = "SIOPBO"; 1289 }; 1290 1291 pinctrl_siopwreq_default: siopwreq_default { 1292 function = "SIOPWREQ"; 1293 groups = "SIOPWREQ"; 1294 }; 1295 1296 pinctrl_siopwrgd_default: siopwrgd_default { 1297 function = "SIOPWRGD"; 1298 groups = "SIOPWRGD"; 1299 }; 1300 1301 pinctrl_sios3_default: sios3_default { 1302 function = "SIOS3"; 1303 groups = "SIOS3"; 1304 }; 1305 1306 pinctrl_sios5_default: sios5_default { 1307 function = "SIOS5"; 1308 groups = "SIOS5"; 1309 }; 1310 1311 pinctrl_siosci_default: siosci_default { 1312 function = "SIOSCI"; 1313 groups = "SIOSCI"; 1314 }; 1315 1316 pinctrl_spi1_default: spi1_default { 1317 function = "SPI1"; 1318 groups = "SPI1"; 1319 }; 1320 1321 pinctrl_spi1debug_default: spi1debug_default { 1322 function = "SPI1DEBUG"; 1323 groups = "SPI1DEBUG"; 1324 }; 1325 1326 pinctrl_spi1passthru_default: spi1passthru_default { 1327 function = "SPI1PASSTHRU"; 1328 groups = "SPI1PASSTHRU"; 1329 }; 1330 1331 pinctrl_spics1_default: spics1_default { 1332 function = "SPICS1"; 1333 groups = "SPICS1"; 1334 }; 1335 1336 pinctrl_timer3_default: timer3_default { 1337 function = "TIMER3"; 1338 groups = "TIMER3"; 1339 }; 1340 1341 pinctrl_timer4_default: timer4_default { 1342 function = "TIMER4"; 1343 groups = "TIMER4"; 1344 }; 1345 1346 pinctrl_timer5_default: timer5_default { 1347 function = "TIMER5"; 1348 groups = "TIMER5"; 1349 }; 1350 1351 pinctrl_timer6_default: timer6_default { 1352 function = "TIMER6"; 1353 groups = "TIMER6"; 1354 }; 1355 1356 pinctrl_timer7_default: timer7_default { 1357 function = "TIMER7"; 1358 groups = "TIMER7"; 1359 }; 1360 1361 pinctrl_timer8_default: timer8_default { 1362 function = "TIMER8"; 1363 groups = "TIMER8"; 1364 }; 1365 1366 pinctrl_txd1_default: txd1_default { 1367 function = "TXD1"; 1368 groups = "TXD1"; 1369 }; 1370 1371 pinctrl_txd2_default: txd2_default { 1372 function = "TXD2"; 1373 groups = "TXD2"; 1374 }; 1375 1376 pinctrl_txd3_default: txd3_default { 1377 function = "TXD3"; 1378 groups = "TXD3"; 1379 }; 1380 1381 pinctrl_txd4_default: txd4_default { 1382 function = "TXD4"; 1383 groups = "TXD4"; 1384 }; 1385 1386 pinctrl_uart6_default: uart6_default { 1387 function = "UART6"; 1388 groups = "UART6"; 1389 }; 1390 1391 pinctrl_usbcki_default: usbcki_default { 1392 function = "USBCKI"; 1393 groups = "USBCKI"; 1394 }; 1395 1396 pinctrl_usb2h_default: usb2h_default { 1397 function = "USB2H1"; 1398 groups = "USB2H1"; 1399 }; 1400 1401 pinctrl_usb2d_default: usb2d_default { 1402 function = "USB2D1"; 1403 groups = "USB2D1"; 1404 }; 1405 1406 pinctrl_vgabios_rom_default: vgabios_rom_default { 1407 function = "VGABIOS_ROM"; 1408 groups = "VGABIOS_ROM"; 1409 }; 1410 1411 pinctrl_vgahs_default: vgahs_default { 1412 function = "VGAHS"; 1413 groups = "VGAHS"; 1414 }; 1415 1416 pinctrl_vgavs_default: vgavs_default { 1417 function = "VGAVS"; 1418 groups = "VGAVS"; 1419 }; 1420 1421 pinctrl_vpi18_default: vpi18_default { 1422 function = "VPI18"; 1423 groups = "VPI18"; 1424 }; 1425 1426 pinctrl_vpi24_default: vpi24_default { 1427 function = "VPI24"; 1428 groups = "VPI24"; 1429 }; 1430 1431 pinctrl_vpi30_default: vpi30_default { 1432 function = "VPI30"; 1433 groups = "VPI30"; 1434 }; 1435 1436 pinctrl_vpo12_default: vpo12_default { 1437 function = "VPO12"; 1438 groups = "VPO12"; 1439 }; 1440 1441 pinctrl_vpo24_default: vpo24_default { 1442 function = "VPO24"; 1443 groups = "VPO24"; 1444 }; 1445 1446 pinctrl_wdtrst1_default: wdtrst1_default { 1447 function = "WDTRST1"; 1448 groups = "WDTRST1"; 1449 }; 1450 1451 pinctrl_wdtrst2_default: wdtrst2_default { 1452 function = "WDTRST2"; 1453 groups = "WDTRST2"; 1454 }; 1455}; 1456