/openbmc/linux/drivers/clk/visconti/ |
H A D | clkc-tmpv770x.c | 35 { TMPV770X_CLK_PIPLL1_DIV4, "pipll1_div4", "pipll1", 0, 1, 4, }, 37 { TMPV770X_CLK_PIPLL1_DIV2, "pipll1_div2", "pipll1", 0, 1, 2, }, 39 { TMPV770X_CLK_PIPLL1_DIV1, "pipll1_div1", "pipll1", 0, 1, 1, }, 42 { TMPV770X_CLK_PIDNNPLL_DIV1, "pidnnpll_div1", "pidnnpll", 0, 1, 1, }, 43 { TMPV770X_CLK_PIREFCLK, "pirefclk", "osc2-clk", 0, 1, 1, }, 44 { TMPV770X_CLK_WDTCLK, "wdtclk", "osc2-clk", 0, 1, 1, }, 51 CLK_SET_RATE_PARENT, 0x34, 0x134, 4, 200, 55 CLK_SET_RATE_PARENT, 0x34, 0x134, 5, 20, 59 CLK_SET_RATE_PARENT, 0x34, 0x134, 6, 10, 63 CLK_SET_RATE_PARENT, 0x34, 0x134, 7, 4, [all …]
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/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt76x2/ |
H A D | usb_init.c | 30 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) | BIT(16)); in mt76x2u_power_on_rf_patch() 33 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1c), 0xff); in mt76x2u_power_on_rf_patch() 34 mt76_set(dev, MT_VEND_ADDR(CFG, 0x1c), 0x30); in mt76x2u_power_on_rf_patch() 36 mt76_wr(dev, MT_VEND_ADDR(CFG, 0x14), 0x484f); in mt76x2u_power_on_rf_patch() 39 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(17)); in mt76x2u_power_on_rf_patch() 42 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(16)); in mt76x2u_power_on_rf_patch() 45 mt76_set(dev, MT_VEND_ADDR(CFG, 0x14c), BIT(19) | BIT(20)); in mt76x2u_power_on_rf_patch() 50 int shift = unit ? 8 : 0; in mt76x2u_power_on_rf() 54 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) << shift); in mt76x2u_power_on_rf() 58 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), val); in mt76x2u_power_on_rf() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | qcom,msm8996-qmp-pcie-phy.yaml | 57 "^phy@[0-9a-f]+$": 92 const: 0 98 const: 0 130 reg = <0x34000 0x488>; 133 ranges = <0x0 0x34000 0x4000>; 149 reg = <0x1000 0x130>, 150 <0x1200 0x200>, 151 <0x1400 0x1dc>; 156 #clock-cells = <0>; 159 #phy-cells = <0>; [all …]
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/openbmc/linux/drivers/phy/qualcomm/ |
H A D | phy-qcom-qmp-pcie-qhp.h | 10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c [all …]
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H A D | phy-qcom-qmp-qserdes-txrx-v4.h | 10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000 11 #define QSERDES_V4_TX_BIST_INVERT 0x004 12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008 13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c 14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010 15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014 16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018 17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c 18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020 19 #define QSERDES_V4_TX_TX_BAND 0x024 [all …]
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H A D | phy-qcom-qmp-qserdes-txrx-v5.h | 11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000 12 #define QSERDES_V5_TX_BIST_INVERT 0x004 13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008 14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c 15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010 16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014 17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018 18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c 19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020 20 #define QSERDES_V5_TX_TX_BAND 0x024 [all …]
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H A D | phy-qcom-qmp-qserdes-pll.h | 10 #define QSERDES_PLL_BG_TIMER 0x00c 11 #define QSERDES_PLL_SSC_PER1 0x01c 12 #define QSERDES_PLL_SSC_PER2 0x020 13 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 14 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 15 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c 16 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 17 #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c 18 #define QSERDES_PLL_CLK_ENABLE1 0x040 19 #define QSERDES_PLL_SYS_CLK_CTRL 0x044 [all …]
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/openbmc/linux/drivers/pinctrl/mediatek/ |
H A D | pinctrl-mt2701.c | 38 /* 0E4E8SR 4/8/12/16 */ 40 /* 0E2E4SR 2/4/6/8 */ 43 MTK_DRV_GRP(2, 16, 0, 2, 2) 47 MTK_PIN_DRV_GRP(0, 0xf50, 0, 1), 48 MTK_PIN_DRV_GRP(1, 0xf50, 0, 1), 49 MTK_PIN_DRV_GRP(2, 0xf50, 0, 1), 50 MTK_PIN_DRV_GRP(3, 0xf50, 0, 1), 51 MTK_PIN_DRV_GRP(4, 0xf50, 0, 1), 52 MTK_PIN_DRV_GRP(5, 0xf50, 0, 1), 53 MTK_PIN_DRV_GRP(6, 0xf50, 0, 1), [all …]
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H A D | pinctrl-mt7623.c | 13 #define PIN_BOND_REG0 0xb10 14 #define PIN_BOND_REG1 0xf20 15 #define PIN_BOND_REG2 0xef0 16 #define BOND_PCIE_CLR (0x77 << 3) 17 #define BOND_I2S_CLR 0x3 18 #define BOND_MSDC0E_CLR 0x1 21 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \ 25 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \ 26 _x_bits, 16, 0) 29 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \ [all …]
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/openbmc/linux/Documentation/dev-tools/ |
H A D | ubsan.rst | 22 CPU: 0 PID: 0 Comm: swapper Not tainted 4.4.0-rc1+ #26 27 [<ffffffff815e6cd6>] dump_stack+0x45/0x5f 28 [<ffffffff8163a5ed>] ubsan_epilogue+0xd/0x40 29 [<ffffffff8163ac2b>] __ubsan_handle_shift_out_of_bounds+0xeb/0x130 30 [<ffffffff815f0001>] ? radix_tree_gang_lookup_slot+0x51/0x150 31 [<ffffffff8173c586>] _mix_pool_bytes+0x1e6/0x480 32 [<ffffffff83105653>] ? dmi_walk_early+0x48/0x5c 33 [<ffffffff8173c881>] add_device_randomness+0x61/0x130 34 [<ffffffff83105b35>] ? dmi_save_one_device+0xaa/0xaa 35 [<ffffffff83105653>] dmi_walk_early+0x48/0x5c [all …]
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/openbmc/qemu/linux-user/loongarch64/ |
H A D | vdso-asmoffset.h | 1 #define sizeof_rt_sigframe 0x240 2 #define sizeof_sigcontext 0x110 3 #define sizeof_sctx_info 0x10 5 #define offsetof_sigcontext 0x130 6 #define offsetof_sigcontext_pc 0 8 #define offsetof_fpucontext_fr 0
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/openbmc/qemu/linux-user/riscv/ |
H A D | vdso-asmoffset.h | 2 # define sizeof_rt_sigframe 0x2b0 3 # define offsetof_uc_mcontext 0x120 4 # define offsetof_freg0 0x80 6 # define sizeof_rt_sigframe 0x340 7 # define offsetof_uc_mcontext 0x130 8 # define offsetof_freg0 0x100
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/openbmc/linux/drivers/gpu/drm/arm/display/komeda/d71/ |
H A D | d71_regs.h | 11 #define BLK_BLOCK_INFO 0x000 12 #define BLK_PIPELINE_INFO 0x004 13 #define BLK_MAX_LINE_SIZE 0x008 14 #define BLK_VALID_INPUT_ID0 0x020 15 #define BLK_OUTPUT_ID0 0x060 16 #define BLK_INPUT_ID0 0x080 17 #define BLK_IRQ_RAW_STATUS 0x0A0 18 #define BLK_IRQ_CLEAR 0x0A4 19 #define BLK_IRQ_MASK 0x0A8 20 #define BLK_IRQ_STATUS 0x0AC [all …]
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/openbmc/u-boot/arch/arc/cpu/arcv1/ |
H A D | ivt.S | 10 j _start /* 0 - 0x000 */ 11 j memory_error /* 1 - 0x008 */ 12 j instruction_error /* 2 - 0x010 */ 16 j interrupt_handler /* 3:31 - 0x018:0xF8 */ 19 j EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */ 20 j EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */ 21 j EV_TLBMissD /* 0x110, Data TLB miss (0x22) */ 22 j EV_TLBProtV /* 0x118, Protection Violation (0x23) 24 j EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */ 25 j EV_Trap /* 0x128, Trap exception (0x25) */ [all …]
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/openbmc/linux/drivers/tty/serial/8250/ |
H A D | 8250_boca.c | 13 SERIAL8250_PORT(0x100, 12), 14 SERIAL8250_PORT(0x108, 12), 15 SERIAL8250_PORT(0x110, 12), 16 SERIAL8250_PORT(0x118, 12), 17 SERIAL8250_PORT(0x120, 12), 18 SERIAL8250_PORT(0x128, 12), 19 SERIAL8250_PORT(0x130, 12), 20 SERIAL8250_PORT(0x138, 12), 21 SERIAL8250_PORT(0x140, 12), 22 SERIAL8250_PORT(0x148, 12), [all …]
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/openbmc/u-boot/include/dt-bindings/clock/ |
H A D | am3.h | 16 #define AM3_CLKCTRL_OFFSET 0x0 22 #define AM3_L4_PER_CLKCTRL_OFFSET 0x14 24 #define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) 25 #define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) 26 #define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) 27 #define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) 28 #define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) 29 #define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) 30 #define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) 31 #define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-tegra/ |
H A D | usb.h | 12 /* 0x000 */ 18 /* 0x010 */ 23 /* 0x020 */ 26 /* 0x100 */ 33 /* 0x120 */ 39 /* 0x130 */ 42 /* 0x140 */ 48 /* 0x150 */ 54 /* 0x160 */ 60 /* 0x170 */ [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | vf610-pinfunc.h | 18 #define ALT0 0x0 19 #define ALT1 0x1 20 #define ALT2 0x2 21 #define ALT3 0x3 22 #define ALT4 0x4 23 #define ALT5 0x5 24 #define ALT6 0x6 25 #define ALT7 0x7 28 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 29 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 [all …]
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/openbmc/linux/arch/sh/drivers/pci/ |
H A D | pci-sh7780.h | 13 #define PCIECR 0xFE000008 14 #define PCIECR_ENBL 0x01 17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */ 18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */ 20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */ 23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */ 24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */ 25 #define SH7780_PCIAIR 0x11C /* Error Address Register */ 26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */ 27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */ [all …]
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/openbmc/linux/drivers/char/mwave/ |
H A D | README | 8 0x0001 mwavedd api tracing 9 0x0002 smapi api tracing 10 0x0004 3780i tracing 11 0x0008 tp3780i tracing 22 mwave_3780i_io=0x130/0x350/0x0070/0xDB0 32 mwave_uart_io=0x3f8/0x2f8/0x3E8/0x2E8 39 insmod mwave mwave_3780i_irq=10 mwave_3780i_io=0x0130 mwave_uart_irq=3 mwave_uart_io=0x2f8
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/openbmc/linux/arch/mips/include/asm/ |
H A D | hpet.h | 9 #define HPET_ID 0x000 10 #define HPET_PERIOD 0x004 11 #define HPET_CFG 0x010 12 #define HPET_STATUS 0x020 13 #define HPET_COUNTER 0x0f0 15 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n) 16 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n) 17 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n) 19 #define HPET_T0_IRS 0x001 20 #define HPET_T1_IRS 0x002 [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/vf/ |
H A D | vf610-pinfunc.h | 14 #define ALT0 0x0 15 #define ALT1 0x1 16 #define ALT2 0x2 17 #define ALT3 0x3 18 #define ALT4 0x4 19 #define ALT5 0x5 20 #define ALT6 0x6 21 #define ALT7 0x7 24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 [all …]
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/openbmc/linux/drivers/clk/mediatek/ |
H A D | reset.h | 15 #define INFRA_RST0_SET_OFFSET 0x120 16 #define INFRA_RST1_SET_OFFSET 0x130 17 #define INFRA_RST2_SET_OFFSET 0x140 18 #define INFRA_RST3_SET_OFFSET 0x150 19 #define INFRA_RST4_SET_OFFSET 0x730 28 MTK_RST_SIMPLE = 0, 67 * Return: 0 on success and errorno otherwise. 77 * Return: 0 on success and errorno otherwise.
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/openbmc/linux/arch/arm64/boot/dts/broadcom/stingray/ |
H A D | stingray-pcie.dtsi | 8 reg = <0 0x60400000 0 0x1000>; 11 bus-range = <0x0 0x1>; 16 ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>; 20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */ 21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */ 22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */ 23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */ 24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */ 25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */ 26 <0x103 &gic_its 0x2180 0x1>, /* PF3 */ [all …]
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/openbmc/linux/drivers/gpu/drm/logicvc/ |
H A D | logicvc_regs.h | 15 #define LOGICVC_HSYNC_FRONT_PORCH_REG 0x00 16 #define LOGICVC_HSYNC_REG 0x08 17 #define LOGICVC_HSYNC_BACK_PORCH_REG 0x10 18 #define LOGICVC_HRES_REG 0x18 19 #define LOGICVC_VSYNC_FRONT_PORCH_REG 0x20 20 #define LOGICVC_VSYNC_REG 0x28 21 #define LOGICVC_VSYNC_BACK_PORCH_REG 0x30 22 #define LOGICVC_VRES_REG 0x38 24 #define LOGICVC_CTRL_REG 0x40 32 #define LOGICVC_CTRL_HSYNC_ENABLE BIT(0) [all …]
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