1*87d71378SDmitry Baryshkov /* SPDX-License-Identifier: GPL-2.0 */ 2*87d71378SDmitry Baryshkov /* 3*87d71378SDmitry Baryshkov * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4*87d71378SDmitry Baryshkov */ 5*87d71378SDmitry Baryshkov 6*87d71378SDmitry Baryshkov #ifndef QCOM_PHY_QMP_PCIE_QHP_H_ 7*87d71378SDmitry Baryshkov #define QCOM_PHY_QMP_PCIE_QHP_H_ 8*87d71378SDmitry Baryshkov 9*87d71378SDmitry Baryshkov /* PCIE GEN3 COM registers */ 10*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 11*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 12*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 13*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 14*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 15*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 16*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 17*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 18*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 19*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 20*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 21*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 22*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 23*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 24*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 25*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 26*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 27*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 28*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 29*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 30*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 31*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 32*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 33*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 34*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 35*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 36*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 37*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 38*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 39*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 40*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 41*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 42*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 43*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 44*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 45*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 46*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 47*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 48*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 49*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 50*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 51*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 52*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 53*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 54*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 55*87d71378SDmitry Baryshkov 56*87d71378SDmitry Baryshkov /* PCIE GEN3 QHP Lane registers */ 57*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 58*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 59*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 60*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 61*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 62*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 63*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 64*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 65*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 66*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 67*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 68*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 69*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 70*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 71*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 72*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 73*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 74*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 75*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 76*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 77*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 78*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 79*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 80*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 81*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 82*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 83*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 84*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 85*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 86*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 87*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 88*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 89*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 90*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 91*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 92*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 93*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 94*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 95*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 96*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 97*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 98*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 99*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 100*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 101*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 102*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 103*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 104*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 105*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 106*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 107*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 108*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 109*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 110*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 111*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 112*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 113*87d71378SDmitry Baryshkov 114*87d71378SDmitry Baryshkov /* PCIE GEN3 PCS registers */ 115*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 116*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 117*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 118*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 119*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 120*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 121*87d71378SDmitry Baryshkov #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 122*87d71378SDmitry Baryshkov 123*87d71378SDmitry Baryshkov #endif 124