132d2cf53SDmitry Baryshkov /* SPDX-License-Identifier: GPL-2.0 */ 232d2cf53SDmitry Baryshkov /* 332d2cf53SDmitry Baryshkov * Copyright (c) 2017, The Linux Foundation. All rights reserved. 432d2cf53SDmitry Baryshkov */ 532d2cf53SDmitry Baryshkov 632d2cf53SDmitry Baryshkov #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_H_ 732d2cf53SDmitry Baryshkov #define QCOM_PHY_QMP_QSERDES_TXRX_V4_H_ 832d2cf53SDmitry Baryshkov 932d2cf53SDmitry Baryshkov /* Only for QMP V4 PHY - TX registers */ 10*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000 11*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_BIST_INVERT 0x004 1232d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008 1332d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c 14*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010 1532d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_TX_DRV_LVL 0x014 16*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018 1732d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c 1832d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020 1932d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_TX_BAND 0x024 20*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_SLEW_CNTL 0x028 2132d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_INTERFACE_SELECT 0x02c 22*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_LPB_EN 0x030 2332d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x034 2432d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x038 2532d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x03c 2632d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x040 27*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_PERL_LENGTH1 0x044 28*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_PERL_LENGTH2 0x048 29*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_SERDES_BYP_EN_OUT 0x04c 30*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_DEBUG_BUS_SEL 0x050 3132d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x054 3232d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x058 3332d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_TX_POL_INV 0x05c 3432d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x060 35*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_BIST_PATTERN1 0x064 36*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_BIST_PATTERN2 0x068 37*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_BIST_PATTERN3 0x06c 38*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_BIST_PATTERN4 0x070 39*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_BIST_PATTERN5 0x074 40*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_BIST_PATTERN6 0x078 41*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_BIST_PATTERN7 0x07c 42*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_BIST_PATTERN8 0x080 4332d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_LANE_MODE_1 0x084 4432d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_LANE_MODE_2 0x088 45*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_LANE_MODE_3 0x08c 46*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_ATB_SEL1 0x090 47*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_ATB_SEL2 0x094 48*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_RCV_DETECT_LVL 0x098 4932d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x09c 50*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_PRBS_SEED1 0x0a0 51*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_PRBS_SEED2 0x0a4 52*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_PRBS_SEED3 0x0a8 53*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_PRBS_SEED4 0x0ac 54*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_RESET_GEN 0x0b0 55*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_RESET_GEN_MUXES 0x0b4 5632d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0x0b8 5732d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_TX_INTERFACE_MODE 0x0bc 58*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_PWM_CTRL 0x0c0 59*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_PWM_ENCODED_OR_DATA 0x0c4 60*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND2 0x0c8 61*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND2 0x0cc 62*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND2 0x0d0 63*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND2 0x0d4 6432d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x0d8 6532d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x0dc 6632d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x0e0 6732d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x0e4 6832d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_VMODE_CTRL1 0x0e8 69*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_ALOG_OBSV_BUS_CTRL_1 0x0ec 70*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_BIST_STATUS 0x0f0 71*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_BIST_ERROR_COUNT1 0x0f4 72*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_BIST_ERROR_COUNT2 0x0f8 73*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_ALOG_OBSV_BUS_STATUS_1 0x0fc 74*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_LANE_DIG_CONFIG 0x100 7532d2cf53SDmitry Baryshkov #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 76*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_PRE_EMPH 0x108 77*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_SW_RESET 0x10c 78*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_DCC_OFFSET 0x110 79*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_DIG_BKUP_CTRL 0x114 80*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_DEBUG_BUS0 0x118 81*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_DEBUG_BUS1 0x11c 82*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_DEBUG_BUS2 0x120 83*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_DEBUG_BUS3 0x124 84*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_READ_EQCODE 0x128 85*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_READ_OFFSETCODE 0x12c 86*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_IA_ERROR_COUNTER_LOW 0x130 87*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_IA_ERROR_COUNTER_HIGH 0x134 88*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_VGA_READ_CODE 0x138 89*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_VTH_READ_CODE 0x13c 90*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_DFE_TAP1_READ_CODE 0x140 91*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_DFE_TAP2_READ_CODE 0x144 92*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_IDAC_STATUS_I 0x148 93*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_IDAC_STATUS_IBAR 0x14c 94*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_IDAC_STATUS_Q 0x150 95*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_IDAC_STATUS_QBAR 0x154 96*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_IDAC_STATUS_A 0x158 97*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_IDAC_STATUS_ABAR 0x15c 98*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_IDAC_STATUS_SM_ON 0x160 99*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_IDAC_STATUS_CAL_DONE 0x164 100*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_IDAC_STATUS_SIGNERROR 0x168 101*1195c1daSDmitry Baryshkov #define QSERDES_V4_TX_DCC_CAL_STATUS 0x16c 10232d2cf53SDmitry Baryshkov 10332d2cf53SDmitry Baryshkov /* Only for QMP V4 PHY - RX registers */ 104*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_UCDR_FO_GAIN_HALF 0x000 105*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_UCDR_FO_GAIN_QUARTER 0x004 10632d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 107*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_UCDR_SO_GAIN_HALF 0x00c 108*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_UCDR_SO_GAIN_QUARTER 0x010 10932d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 110*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_UCDR_SVS_FO_GAIN_HALF 0x018 111*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c 112*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_UCDR_SVS_FO_GAIN 0x020 113*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_UCDR_SVS_SO_GAIN_HALF 0x024 114*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 115*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_UCDR_SVS_SO_GAIN 0x02c 11632d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 11732d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 118*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_UCDR_FO_TO_SO_DELAY 0x038 11932d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 12032d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 12132d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 12232d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 12332d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c 12432d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 12532d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 12632d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 127*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_AUX_CONTROL 0x05c 12832d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 12932d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 13032d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 131*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_AC_JTAG_INITP 0x06c 132*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_AC_JTAG_INITN 0x070 133*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_AC_JTAG_LVL 0x074 13432d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 135*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_AC_JTAG_RESET 0x07c 13632d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_TERM_BW 0x080 137*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_RCVR_IQ_EN 0x084 138*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_IDAC_I_DC_OFFSETS 0x088 139*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c 140*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_IDAC_Q_DC_OFFSETS 0x090 141*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094 142*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_IDAC_A_DC_OFFSETS 0x098 143*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c 144*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_IDAC_EN 0x0a0 145*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_IDAC_ENABLES 0x0a4 146*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_IDAC_SIGN 0x0a8 147*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_HIGHZ_HIGHRATE 0x0ac 148*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0 149*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_DFE_1 0x0b4 150*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_DFE_2 0x0b8 151*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_DFE_3 0x0bc 152*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_DFE_4 0x0c0 153*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_TX_ADAPT_PRE_THRESH1 0x0c4 154*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_TX_ADAPT_PRE_THRESH2 0x0c8 155*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_TX_ADAPT_POST_THRESH 0x0cc 156*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_TX_ADAPT_MAIN_THRESH 0x0d0 15732d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 15832d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 15932d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_GM_CAL 0x0dc 160*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_VGA_GAIN2_LSB 0x0e0 161*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_VGA_GAIN2_MSB 0x0e4 16232d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 16332d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 16432d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 16532d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 16632d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 16732d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 16832d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 169*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_IDAC_ACCUMULATOR 0x104 170*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_EQ_OFFSET_LSB 0x108 171*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_EQ_OFFSET_MSB 0x10c 17232d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 17332d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 17432d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_SIGDET_ENABLES 0x118 17532d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 17632d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_SIGDET_LVL 0x120 17732d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 17832d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_BAND 0x128 179*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_CDR_FREEZE_UP_DN 0x12c 180*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_CDR_RESET_OVERRIDE 0x130 181*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_INTERFACE_MODE 0x134 182*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_JITTER_GEN_MODE 0x138 183*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_SJ_AMP1 0x13c 184*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_SJ_AMP2 0x140 185*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_SJ_PER1 0x144 186*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_SJ_PER2 0x148 187*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_PPM_OFFSET1 0x14c 188*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_PPM_OFFSET2 0x150 189*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_SIGN_PPM_PERIOD1 0x154 190*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_SIGN_PPM_PERIOD2 0x158 191*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_PWM_ENABLE_AND_DATA 0x15c 192*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x160 193*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x164 194*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x168 195*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x16c 19632d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 19732d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 19832d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 19932d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 20032d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 20132d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 20232d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 20332d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 20432d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 20532d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 20632d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 20732d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 20832d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 20932d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 21032d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 211*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_PHPRE_CTRL 0x1ac 212*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_PHPRE_INITVAL 0x1b0 21332d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 21432d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 21532d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 216*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_DCC_CTRL2 0x1c0 21732d2cf53SDmitry Baryshkov #define QSERDES_V4_RX_VTH_CODE 0x1c4 218*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_VTH_MIN_THRESH 0x1c8 219*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_VTH_MAX_THRESH 0x1cc 220*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_ALOG_OBSV_BUS_CTRL_1 0x1d0 221*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_PI_CTRL1 0x1d4 222*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_PI_CTRL2 0x1d8 223*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_PI_QUAD 0x1dc 224*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_IDATA1 0x1e0 225*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_IDATA2 0x1e4 226*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_AUX_DATA1 0x1e8 227*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_AUX_DATA2 0x1ec 228*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_AC_JTAG_OUTP 0x1f0 229*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_AC_JTAG_OUTN 0x1f4 230*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_RX_SIGDET 0x1f8 231*1195c1daSDmitry Baryshkov #define QSERDES_V4_RX_ALOG_OBSV_BUS_STATUS_1 0x1fc 23232d2cf53SDmitry Baryshkov 23332d2cf53SDmitry Baryshkov #endif 234