Home
last modified time | relevance | path

Searched +full:0 +full:x120 (Results 1 – 25 of 738) sorted by relevance

12345678910>>...30

/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-var-som.dtsi20 reg = <0x0 0x40000000 0 0x40000000>;
26 pinctrl-0 = <&pinctrl_reg_eth_phy>;
54 pinctrl-0 = <&pinctrl_ecspi1>;
56 <&gpio1 0 GPIO_ACTIVE_LOW>;
62 touchscreen@0 {
63 reg = <0>;
66 pinctrl-0 = <&pinctrl_restouch>;
90 pinctrl-0 = <&pinctrl_fec1>;
100 #size-cells = <0>;
120 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
/openbmc/linux/Documentation/dev-tools/
H A Dubsan.rst22 CPU: 0 PID: 0 Comm: swapper Not tainted 4.4.0-rc1+ #26
27 [<ffffffff815e6cd6>] dump_stack+0x45/0x5f
28 [<ffffffff8163a5ed>] ubsan_epilogue+0xd/0x40
29 [<ffffffff8163ac2b>] __ubsan_handle_shift_out_of_bounds+0xeb/0x130
30 [<ffffffff815f0001>] ? radix_tree_gang_lookup_slot+0x51/0x150
31 [<ffffffff8173c586>] _mix_pool_bytes+0x1e6/0x480
32 [<ffffffff83105653>] ? dmi_walk_early+0x48/0x5c
33 [<ffffffff8173c881>] add_device_randomness+0x61/0x130
34 [<ffffffff83105b35>] ? dmi_save_one_device+0xaa/0xaa
35 [<ffffffff83105653>] dmi_walk_early+0x48/0x5c
[all …]
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt7622.c217 .set_ofs = 0x120,
218 .clr_ofs = 0x120,
219 .sta_ofs = 0x120,
223 .set_ofs = 0x128,
224 .clr_ofs = 0x128,
225 .sta_ofs = 0x128,
229 .set_ofs = 0x8,
230 .clr_ofs = 0x10,
231 .sta_ofs = 0x18,
235 .set_ofs = 0xC,
[all …]
H A Dclk-mt6795-topckgen.c17 * So we model these clocks' rate as 0, to denote it's not an actual rate.
19 #define DUMMY_RATE 0
23 (_reg + 0x4), (_reg + 0x8), _shift, _width, \
24 _gate, 0, -1, _flags)
362 FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0),
363 FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0),
364 FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0),
365 FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0),
370 FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0),
371 FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0),
[all …]
H A Dclk-mt8173-topckgen.c18 * So we model these clocks' rate as 0, to denote it's not an actual rate.
20 #define DUMMY_RATE 0
24 (_reg + 0x4), (_reg + 0x8), _shift, _width, \
25 _gate, 0, -1, _flags)
437 FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0),
438 FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0),
439 FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0),
440 FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0),
445 FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0),
446 FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0),
[all …]
/openbmc/u-boot/drivers/clk/renesas/
H A Dr8a7795-cpg-mssr.c96 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
97 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
98 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
99 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
101 DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238),
114 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
275 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
276 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
277 * 0 0 1 0 Prohibited setting
278 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
[all …]
H A Dr8a7796-cpg-mssr.c96 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
97 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
98 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
99 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
101 DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238),
248 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
249 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
250 * 0 0 1 0 Prohibited setting
251 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
252 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
[all …]
/openbmc/linux/drivers/clk/renesas/
H A Dr8a774a1-cpg-mssr.c78 DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
100 DEF_GEN3_SDH("sd0h", R8A774A1_CLK_SD0H, CLK_SDSRC, 0x074),
101 DEF_GEN3_SDH("sd1h", R8A774A1_CLK_SD1H, CLK_SDSRC, 0x078),
102 DEF_GEN3_SDH("sd2h", R8A774A1_CLK_SD2H, CLK_SDSRC, 0x268),
103 DEF_GEN3_SDH("sd3h", R8A774A1_CLK_SD3H, CLK_SDSRC, 0x26c),
104 DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, R8A774A1_CLK_SD0H, 0x074),
105 DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, R8A774A1_CLK_SD1H, 0x078),
106 DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268),
107 DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c),
116 DEF_DIV6P1("canfd", R8A774A1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
[all …]
H A Dr8a774e1-cpg-mssr.c78 DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
100 DEF_GEN3_SDH("sd0h", R8A774E1_CLK_SD0H, CLK_SDSRC, 0x074),
101 DEF_GEN3_SDH("sd1h", R8A774E1_CLK_SD1H, CLK_SDSRC, 0x078),
102 DEF_GEN3_SDH("sd2h", R8A774E1_CLK_SD2H, CLK_SDSRC, 0x268),
103 DEF_GEN3_SDH("sd3h", R8A774E1_CLK_SD3H, CLK_SDSRC, 0x26c),
104 DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, R8A774E1_CLK_SD0H, 0x074),
105 DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, R8A774E1_CLK_SD1H, 0x078),
106 DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268),
107 DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c),
117 DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
[all …]
H A Dr8a7796-cpg-mssr.c83 DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
106 DEF_GEN3_SDH("sd0h", R8A7796_CLK_SD0H, CLK_SDSRC, 0x074),
107 DEF_GEN3_SDH("sd1h", R8A7796_CLK_SD1H, CLK_SDSRC, 0x078),
108 DEF_GEN3_SDH("sd2h", R8A7796_CLK_SD2H, CLK_SDSRC, 0x268),
109 DEF_GEN3_SDH("sd3h", R8A7796_CLK_SD3H, CLK_SDSRC, 0x26c),
110 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, R8A7796_CLK_SD0H, 0x074),
111 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, R8A7796_CLK_SD1H, 0x078),
112 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268),
113 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c),
123 DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
[all …]
H A Dr8a7795-cpg-mssr.c81 DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
104 DEF_GEN3_SDH("sd0h", R8A7795_CLK_SD0H, CLK_SDSRC, 0x074),
105 DEF_GEN3_SDH("sd1h", R8A7795_CLK_SD1H, CLK_SDSRC, 0x078),
106 DEF_GEN3_SDH("sd2h", R8A7795_CLK_SD2H, CLK_SDSRC, 0x268),
107 DEF_GEN3_SDH("sd3h", R8A7795_CLK_SD3H, CLK_SDSRC, 0x26c),
108 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, R8A7795_CLK_SD0H, 0x074),
109 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, R8A7795_CLK_SD1H, 0x078),
110 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268),
111 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c),
121 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
[all …]
H A Dr8a774b1-cpg-mssr.c97 DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074),
98 DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078),
99 DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268),
100 DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c),
101 DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074),
102 DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078),
103 DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268),
104 DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c),
113 DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
114 DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
[all …]
H A Dr8a77965-cpg-mssr.c101 DEF_GEN3_SDH("sd0h", R8A77965_CLK_SD0H, CLK_SDSRC, 0x074),
102 DEF_GEN3_SDH("sd1h", R8A77965_CLK_SD1H, CLK_SDSRC, 0x078),
103 DEF_GEN3_SDH("sd2h", R8A77965_CLK_SD2H, CLK_SDSRC, 0x268),
104 DEF_GEN3_SDH("sd3h", R8A77965_CLK_SD3H, CLK_SDSRC, 0x26c),
105 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, R8A77965_CLK_SD0H, 0x074),
106 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, R8A77965_CLK_SD1H, 0x078),
107 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268),
108 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c),
118 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
119 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
[all …]
/openbmc/linux/include/linux/mfd/syscon/
H A Datmel-matrix.h11 #define AT91SAM9260_MATRIX_MCFG 0x00
12 #define AT91SAM9260_MATRIX_SCFG 0x40
13 #define AT91SAM9260_MATRIX_PRS 0x80
14 #define AT91SAM9260_MATRIX_MRCR 0x100
15 #define AT91SAM9260_MATRIX_EBICSA 0x11c
17 #define AT91SAM9261_MATRIX_MRCR 0x0
18 #define AT91SAM9261_MATRIX_SCFG 0x4
19 #define AT91SAM9261_MATRIX_TCR 0x24
20 #define AT91SAM9261_MATRIX_EBICSA 0x30
21 #define AT91SAM9261_MATRIX_USBPUCR 0x34
[all …]
/openbmc/linux/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-mediatek-hw.yaml47 #size-cells = <0>;
49 cpu0: cpu@0 {
53 performance-domains = <&performance 0>;
54 reg = <0x000>;
66 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
/openbmc/linux/Documentation/devicetree/bindings/dvfs/
H A Dperformance-domain.yaml37 Number of cells in a performance domain specifier. Typically 0 for nodes
42 enum: [ 0, 1 ]
60 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
71 #size-cells = <0>;
73 cpu@0 {
76 reg = <0x0 0x0>;
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcie-qhp.h10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
[all …]
/openbmc/linux/drivers/media/usb/gspca/
H A Dkonica.c29 #define WHITEBAL_REG 0x01
30 #define BRIGHTNESS_REG 0x02
31 #define SHARPNESS_REG 0x03
32 #define CONTRAST_REG 0x04
33 #define SATURATION_REG 0x05
44 0x00 -> 176x144, cropped
45 0x01 -> 176x144, cropped
46 0x02 -> 176x144, cropped
47 0x03 -> 176x144, cropped
48 0x04 -> 176x144, binned
[all …]
/openbmc/qemu/hw/m68k/
H A Dmcf5206.c33 #define TMR_RST 0x01
34 #define TMR_CLK 0x06
35 #define TMR_FRR 0x08
36 #define TMR_ORI 0x10
37 #define TMR_OM 0x20
38 #define TMR_CE 0xc0
40 #define TER_CAP 0x01
41 #define TER_REF 0x02
45 if ((s->tmr & TMR_ORI) != 0 && (s->ter & TER_REF)) in m5206_timer_update()
53 s->tmr = 0; in m5206_timer_reset()
[all …]
/openbmc/u-boot/include/dt-bindings/clock/
H A Dam3.h16 #define AM3_CLKCTRL_OFFSET 0x0
22 #define AM3_L4_PER_CLKCTRL_OFFSET 0x14
24 #define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14)
25 #define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18)
26 #define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c)
27 #define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24)
28 #define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28)
29 #define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c)
30 #define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30)
31 #define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34)
[all …]
/openbmc/linux/include/dt-bindings/clock/
H A Dam3.h8 #define AM3_CLKCTRL_OFFSET 0x0
12 #define AM3_L4LS_CLKCTRL_OFFSET 0x38
14 #define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38)
15 #define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c)
16 #define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40)
17 #define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44)
18 #define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48)
19 #define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c)
20 #define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50)
21 #define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60)
[all …]
/openbmc/qemu/pc-bios/s390-ccw/
H A Ds390-arch.h28 #define PSW_MASK_IOINT 0x0200000000000000ULL
29 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL
30 #define PSW_MASK_WAIT 0x0002000000000000ULL
31 #define PSW_MASK_EAMODE 0x0000000100000000ULL
32 #define PSW_MASK_BAMODE 0x0000000080000000ULL
33 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL
39 PSWLegacy ipl_psw; /* 0x000 */
40 uint32_t ccw1[2]; /* 0x008 */
42 uint32_t ccw2[2]; /* 0x010 */
48 uint8_t pad1[0x80 - 0x18]; /* 0x018 */
[all …]
/openbmc/u-boot/drivers/sound/
H A Divybridge_sound.c32 return 0; in bd82x6x_azalia_probe()
46 conf = pch_ioctl(pch, PCH_REQ_HDA_CONFIG, NULL, 0); in bd82x6x_azalia_probe()
48 if (conf >= 0) { in bd82x6x_azalia_probe()
49 dm_pci_clrset_config32(dev, 0x120, 7 << 24 | 0xfe, in bd82x6x_azalia_probe()
53 dm_pci_clrset_config16(dev, 0x78, 0, 1 << 1); in bd82x6x_azalia_probe()
57 dm_pci_clrset_config32(dev, 0x114, 0xfe, 0); in bd82x6x_azalia_probe()
60 dm_pci_clrset_config32(dev, 0x120, 0, 1U << 31); in bd82x6x_azalia_probe()
63 dm_pci_clrset_config32(dev, 0xc4, 0, 1 << 1); in bd82x6x_azalia_probe()
64 dm_pci_clrset_config8(dev, 0x43, 0, 1 << 6); in bd82x6x_azalia_probe()
67 dm_pci_clrset_config32(dev, 0xc4, 0, 1 << 13); in bd82x6x_azalia_probe()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/ti/
H A Dkeystone-navigator-dma.txt17 |-> DMA instance #0
64 knav_dmas: knav_dmas@0 {
70 ti,navigator-cloud-address = <0x23a80000 0x23a90000
71 0x23aa0000 0x23ab0000>;
73 dma_gbe: dma_gbe@0 {
74 reg = <0x2004000 0x100>,
75 <0x2004400 0x120>,
76 <0x2004800 0x300>,
77 <0x2004c00 0x120>,
78 <0x2005000 0x400>;
[all …]
/openbmc/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
[all …]

12345678910>>...30