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12

/openbmc/linux/Documentation/devicetree/bindings/media/
H A Drenesas,jpu.yaml60 reg = <0xfe980000 0x10300>;
/openbmc/u-boot/arch/arm/mach-kirkwood/include/mach/
H A Dsoc.h16 #define INTREG_BASE 0xd0000000
18 #define KW_OFFSET_REG (INTREG_BASE + 0x20080)
21 #define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470))
22 #define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478))
24 #define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500))
25 #define KW_TWSI_BASE (KW_REGISTER(0x11000))
26 #define KW_UART0_BASE (KW_REGISTER(0x12000))
27 #define KW_UART1_BASE (KW_REGISTER(0x12100))
28 #define KW_MPP_BASE (KW_REGISTER(0x10000))
29 #define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100))
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dkirkwood-6281.dtsi12 bus-range = <0x00 0xff>;
15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
19 pcie0: pcie@1,0 {
21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
22 reg = <0x0800 0 0 0 0>;
26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
27 0x81000000 0 0 0x81000000 0x1 0 1 0>;
28 bus-range = <0x00 0xff>;
[all …]
H A Dkirkwood-6192.dtsi12 bus-range = <0x00 0xff>;
15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
19 pcie0: pcie@1,0 {
21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
22 reg = <0x0800 0 0 0 0>;
26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
27 0x81000000 0 0 0x81000000 0x1 0 1 0>;
28 bus-range = <0x00 0xff>;
[all …]
H A Darmada-370-xp.dtsi68 #size-cells = <0>;
69 cpu@0 {
72 reg = <0>;
86 pcie-mem-aperture = <0xf8000000 0x7e00000>;
87 pcie-io-aperture = <0xffe00000 0x100000>;
91 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
92 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
95 clocks = <&coreclk 0>;
101 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
102 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
[all …]
H A Darmada-375.dtsi71 #clock-cells = <0>;
77 #clock-cells = <0>;
84 #size-cells = <0>;
87 cpu@0 {
90 reg = <0>;
111 pcie-mem-aperture = <0xe0000000 0x8000000>;
112 pcie-io-aperture = <0xe8000000 0x100000>;
116 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
121 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
122 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
[all …]
H A Dr8a7792.dtsi39 #clock-cells = <0>;
41 clock-frequency = <0>;
46 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
69 L2_CA15: cache-controller-0 {
80 #clock-cells = <0>;
82 clock-frequency = <0>;
95 #clock-cells = <0>;
97 clock-frequency = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-6281.dtsi12 bus-range = <0x00 0xff>;
15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
19 pcie0: pcie@1,0 {
21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
22 reg = <0x0800 0 0 0 0>;
26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
27 0x81000000 0 0 0x81000000 0x1 0 1 0>;
28 bus-range = <0x00 0xff>;
[all …]
H A Dkirkwood-6192.dtsi12 bus-range = <0x00 0xff>;
15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
19 pcie0: pcie@1,0 {
21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
22 reg = <0x0800 0 0 0 0>;
26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
27 0x81000000 0 0 0x81000000 0x1 0 1 0>;
28 bus-range = <0x00 0xff>;
[all …]
H A Dkirkwood-6282.dtsi12 bus-range = <0x00 0xff>;
15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
17 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
18 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
19 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
20 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */
21 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>;
23 pcie0: pcie@1,0 {
25 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
[all …]
H A Darmada-370-xp.dtsi29 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
47 pcie-mem-aperture = <0xf8000000 0x7e00000>;
48 pcie-io-aperture = <0xffe00000 0x100000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
[all …]
H A Darmada-375.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
[all …]
/openbmc/linux/drivers/net/ethernet/wangxun/txgbe/
H A Dtxgbe_type.h10 #define TXGBE_DEV_ID_SP1000 0x1001
11 #define TXGBE_DEV_ID_WX1820 0x2001
15 #define TXGBE_ID_SP1000_SFP 0x0000
16 #define TXGBE_ID_WX1820_SFP 0x2000
17 #define TXGBE_ID_SFP 0x00
20 #define TXGBE_ID_SP1000_XAUI 0x1010
21 #define TXGBE_ID_WX1820_XAUI 0x2010
22 #define TXGBE_ID_XAUI 0x10
23 #define TXGBE_ID_SP1000_SGMII 0x1020
24 #define TXGBE_ID_WX1820_SGMII 0x2020
[all …]
/openbmc/linux/sound/pci/au88x0/
H A Dau8820.h19 #define NR_ADB 0x10
20 #define NR_WT 0x20
21 #define NR_SRC 0x10
22 #define NR_A3D 0x00
23 #define NR_MIXIN 0x10
24 #define NR_MIXOUT 0x10
28 #define VORTEX_ADBDMA_STAT 0x105c0 /* read only, subbuffer, DMA pos */
29 #define POS_MASK 0x00000fff
30 #define POS_SHIFT 0x0
31 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
[all …]
/openbmc/linux/drivers/net/ethernet/cavium/thunder/
H A Dthunder_bgx.h10 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026
11 #define PCI_DEVICE_ID_THUNDER_RGX 0xA054
14 #define PCI_SUBSYS_DEVID_88XX_BGX 0xA126
15 #define PCI_SUBSYS_DEVID_81XX_BGX 0xA226
16 #define PCI_SUBSYS_DEVID_81XX_RGX 0xA254
17 #define PCI_SUBSYS_DEVID_83XX_BGX 0xA326
27 #define DEFAULT_PAUSE_TIME 0xFFFF
29 #define BGX_ID_MASK 0x3
30 #define LMAC_ID_MASK 0x3
35 #define BGX_CMRX_CFG 0x00
[all …]
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Dfvp-base-revc.dts15 /memreserve/ 0x80000000 0x00010000;
43 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0 0x000>;
50 i-cache-size = <0x8000>;
53 d-cache-size = <0x8000>;
61 reg = <0x0 0x100>;
63 i-cache-size = <0x8000>;
66 d-cache-size = <0x8000>;
74 reg = <0x0 0x200>;
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_offset.h26 // base address: 0x0
27 … 0x0000 // duplicate
28 … 0x0002 // duplicate
29 … 0x0004 // duplicate
30 … 0x0006 // duplicate
31 … 0x0008 // duplicate
32 … 0x0009 // duplicate
33 … 0x000a // duplicate
34 … 0x000b // duplicate
35 … 0x000c // duplicate
[all …]
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7792.dtsi40 #clock-cells = <0>;
42 clock-frequency = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
71 L2_CA15: cache-controller-0 {
82 #clock-cells = <0>;
84 clock-frequency = <0>;
97 #clock-cells = <0>;
99 clock-frequency = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip06.dtsi23 #size-cells = <0>;
87 reg = <0x10000>;
95 reg = <0x10001>;
103 reg = <0x10002>;
111 reg = <0x10003>;
119 reg = <0x10100>;
127 reg = <0x10101>;
135 reg = <0x10102>;
143 reg = <0x10103>;
151 reg = <0x10200>;
[all …]
/openbmc/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.h26 #define MTK_DSA_PORT_MASK GENMASK(2, 0)
32 #define MTK_TX_DMA_BUF_LEN 0x3fff
33 #define MTK_TX_DMA_BUF_LEN_V2 0xffff
38 #define MTK_DMA_DUMMY_DESC 0xffffffff
62 #define MTK_QRX_OFFSET 0x10
79 #define MTK_FE_GLO_CFG(x) (((x) == MTK_GMAC3_ID) ? 0x24 : 0x00)
83 #define MTK_RST_GL 0x04
84 #define RST_GL_PSE BIT(0)
87 #define MTK_INT_STATUS2 0x08
88 #define MTK_FE_INT_ENABLE 0x0c
[all …]
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov9.dtsi47 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0>;
91 reg = <0x100>;
98 reg = <0x200>;
105 reg = <0x300>;
112 reg = <0x10000>;
119 reg = <0x10100>;
126 reg = <0x10200>;
133 reg = <0x10300>;
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Drv515.c47 0,
59 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); in rv515_ring_start()
65 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start()
67 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); in rv515_ring_start()
69 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); in rv515_ring_start()
70 radeon_ring_write(ring, 0); in rv515_ring_start()
71 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); in rv515_ring_start()
72 radeon_ring_write(ring, 0); in rv515_ring_start()
73 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); in rv515_ring_start()
75 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); in rv515_ring_start()
[all …]
/openbmc/linux/drivers/perf/hisilicon/
H A Dhns3_pmu.c29 #define HNS3_PMU_REG_GLOBAL_CTRL 0x0000
30 #define HNS3_PMU_REG_CLOCK_FREQ 0x0020
31 #define HNS3_PMU_REG_BDF 0x0fe0
32 #define HNS3_PMU_REG_VERSION 0x0fe4
33 #define HNS3_PMU_REG_DEVICE_ID 0x0fe8
35 #define HNS3_PMU_REG_EVENT_OFFSET 0x1000
36 #define HNS3_PMU_REG_EVENT_SIZE 0x1000
37 #define HNS3_PMU_REG_EVENT_CTRL_LOW 0x00
38 #define HNS3_PMU_REG_EVENT_CTRL_HIGH 0x04
39 #define HNS3_PMU_REG_EVENT_INTR_STATUS 0x08
[all …]
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos4.c22 #define SRC_LEFTBUS 0x4200
23 #define DIV_LEFTBUS 0x4500
24 #define GATE_IP_LEFTBUS 0x4800
25 #define E4X12_GATE_IP_IMAGE 0x4930
26 #define CLKOUT_CMU_LEFTBUS 0x4a00
27 #define SRC_RIGHTBUS 0x8200
28 #define DIV_RIGHTBUS 0x8500
29 #define GATE_IP_RIGHTBUS 0x8800
30 #define E4X12_GATE_IP_PERIR 0x8960
31 #define CLKOUT_CMU_RIGHTBUS 0x8a00
[all …]

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