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Searched defs:CONFIG_SYS_DDR_TIMING_2 (Results 1 – 25 of 30) sorted by relevance

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/openbmc/u-boot/include/configs/km/
H A Dkm8321-common.h107 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ macro
H A Dkm8309-common.h143 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ macro
/openbmc/u-boot/include/configs/
H A Dkm8360.h130 #define CONFIG_SYS_DDR_TIMING_2 (\ macro
H A DMPC8349EMDS.h108 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 macro
121 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ macro
H A DMPC8540ADS.h87 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ macro
H A Dsocrates.h86 #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 macro
H A Dmpc8308_p1m.h162 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
H A DMPC8560ADS.h86 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ macro
H A Dve8313.h84 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
H A DMPC8308RDB.h158 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
H A Dids8313.h129 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\ macro
H A DMPC832XEMDS.h118 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
H A DMPC8323ERDB.h108 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
H A Dsbc8349.h98 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ macro
H A Dp1_twr.h103 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de macro
H A DMPC8313ERDB.h145 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
H A DMPC837XERDB.h171 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
H A DUCP1020.h175 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF macro
H A DMPC8315ERDB.h133 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
H A DMPC837XEMDS.h158 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
H A Dhrcon.h149 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
H A DMPC8349ITX.h182 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ macro
H A Dstrider.h149 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
H A DMPC8569MDS.h94 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 macro
H A Dsbc8641d.h127 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 macro

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