Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04 |
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d94604d5 |
| 10-Dec-2018 |
Tom Rini <trini@konsulko.com> |
Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq
Add TFA boot flow for some Layerscape platforms Add support for lx2160a SoC
[trini: Add a bunch of missing MAINTAINERS e
Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq
Add TFA boot flow for some Layerscape platforms Add support for lx2160a SoC
[trini: Add a bunch of missing MAINTAINERS entries] Signed-off-by: Tom Rini <trini@konsulko.com>
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#
10c8aa16 |
| 05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: ls1012aqds: Add TFABOOT support
TFABOOT support includes: - ls1012aqds_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - define BOOTCOMMAN
armv8: ls1012aqds: Add TFABOOT support
TFABOOT support includes: - ls1012aqds_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - define BOOTCOMMAND for TFABOOT
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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e5141cbe |
| 05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: ls1012aqds: fix secure boot compilation
Includes environment.h file in ls1012aqds.c Also, enables pfe validation
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Su
armv8: ls1012aqds: fix secure boot compilation
Includes environment.h file in ls1012aqds.c Also, enables pfe validation
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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Revision tags: v2018.07 |
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83d290c5 |
| 06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So
SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one.
Signed-off-by: Tom Rini <trini@konsulko.com>
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b0af1044 |
| 22-Mar-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-net
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Revision tags: v2018.03 |
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7a8df8ba |
| 08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
board: freescale: ls1012aqds: enable network support on ls1012aqds
This patch enables ethernet support for ls1012aqds.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyu
board: freescale: ls1012aqds: enable network support on ls1012aqds
This patch enables ethernet support for ls1012aqds.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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Revision tags: v2018.01, v2017.11 |
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8a33cb8b |
| 12-Sep-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
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63b2316c |
| 11-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus
CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O cohere
fsl-layerscape: Consolidate registers space defination for CCI-400 bus
CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters.
This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com>
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ce38ebb6 |
| 16-Mar-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
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4961eafc |
| 06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Update early MMU for DDR after initialization
In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updat
armv8: layerscape: Update early MMU for DDR after initialization
In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function.
Signed-off-by: York Sun <york.sun@nxp.com>
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36cc0de0 |
| 06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Rewrite memory reservation
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit a
armv8: layerscape: Rewrite memory reservation
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader.
Signed-off-by: York Sun <york.sun@nxp.com>
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c83a824e |
| 03-Feb-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts: configs/ls1046aqds_defconfig configs/ls1046aqds_nand_defconfig configs/ls1046aqds_qspi_defconfig
Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts: configs/ls1046aqds_defconfig configs/ls1046aqds_nand_defconfig configs/ls1046aqds_qspi_defconfig configs/ls1046aqds_sdcard_ifc_defconfig configs/ls1046aqds_sdcard_qspi_defconfig configs/ls1046ardb_emmc_defconfig configs/ls1046ardb_qspi_defconfig configs/ls1046ardb_sdcard_defconfig
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5b404be6 |
| 30-Jan-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: ls1012a: Add support of PPA
The PPA implements PSCI which requires for power managment.
Added support of PPA for LS1012AQDS, LS1012ARDB and LS1012AFRDM.
Signed-off-by: Hou Zhiqiang <Zhiqian
armv8: ls1012a: Add support of PPA
The PPA implements PSCI which requires for power managment.
Added support of PPA for LS1012AQDS, LS1012ARDB and LS1012AFRDM.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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7d559604 |
| 30-Jan-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
board: freescale: ls1012a: Enable secure DDR on LS1012A platforms
PPA binary needs to be relocated on secure DDR, hence marking out a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag i
board: freescale: ls1012a: Enable secure DDR on LS1012A platforms
PPA binary needs to be relocated on secure DDR, hence marking out a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag is set
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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0675f992 |
| 19-Jan-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
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208e1ae8 |
| 16-Jan-2017 |
Yangbo Lu <yangbo.lu@nxp.com> |
armv8: ls1012a: define esdhc_status_fixup for QDS board
The LS1012AQDS board has a hardware issue. When there is no eMMC adapter card inserted in SDHC2 adapter slot, the command inhibit bits of eSDH
armv8: ls1012a: define esdhc_status_fixup for QDS board
The LS1012AQDS board has a hardware issue. When there is no eMMC adapter card inserted in SDHC2 adapter slot, the command inhibit bits of eSDHC2_PRSSTAT register will never release. This would cause below continious error messages in linux since it uses polling mode to detect card. "mmc1: Controller never released inhibit bit(s)." "mmc1: Controller never released inhibit bit(s)." "mmc1: Controller never released inhibit bit(s)." This patch is to define esdhc_status_fixup function for QDS to disable SDHC2 status if no eMMC adapter card is detected.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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cbe7706a |
| 26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c
Signed-off-by: Tom Rini <trini@konsulko.com>
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1fdcc8df |
| 26-Sep-2016 |
York Sun <york.sun@nxp.com> |
driver: ddr: fsl_mmdc: Pass board parameters through data structure
Instead of using multiple macros, a data structure is used to pass board-specific parameters to MMDC DDR driver.
Signed-off-by: Y
driver: ddr: fsl_mmdc: Pass board parameters through data structure
Instead of using multiple macros, a data structure is used to pass board-specific parameters to MMDC DDR driver.
Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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b9e745bb |
| 26-Aug-2016 |
Shengzhou Liu <Shengzhou.Liu@nxp.com> |
driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012a
This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integra
driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012a
This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future.
Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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b392a6d4 |
| 02-Aug-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
fsl-layerscape: Add workaround for PCIe erratum A010315
As the access to serders protocol unselected PCIe controller will hang. So disable the R/W permission to unselected PCIe controller including
fsl-layerscape: Add workaround for PCIe erratum A010315
As the access to serders protocol unselected PCIe controller will hang. So disable the R/W permission to unselected PCIe controller including its CCSR, IO space and memory space according to the serders protocol field of RCW.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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341238fd |
| 02-Aug-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
arm: fsl-layerscape: move forward the non-secure access permission setup
Move forward the basic non-secure access enable operation, so the subsequent individual device access permission can override
arm: fsl-layerscape: move forward the non-secure access permission setup
Move forward the basic non-secure access enable operation, so the subsequent individual device access permission can override it. And collect the dispersed callers in board level, and then move them to SoC level.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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Revision tags: v2016.07, openbmc-20160624-1 |
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dc557e9a |
| 18-Jun-2016 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
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c41c649c |
| 04-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
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9d044fcb |
| 03-Jun-2016 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: ls1012a: Add support of ls1012aqds board
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance development platform, with a complete debugging environment. The LS1012AQDS board
armv8: ls1012a: Add support of ls1012aqds board
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance development platform, with a complete debugging environment. The LS1012AQDS board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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