1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <i2c.h> 8 #include <fdt_support.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/fsl_serdes.h> 12 #ifdef CONFIG_FSL_LS_PPA 13 #include <asm/arch/ppa.h> 14 #endif 15 #include <asm/arch/fdt.h> 16 #include <asm/arch/mmu.h> 17 #include <asm/arch/soc.h> 18 #include <ahci.h> 19 #include <hwconfig.h> 20 #include <mmc.h> 21 #include <environment.h> 22 #include <scsi.h> 23 #include <fm_eth.h> 24 #include <fsl_esdhc.h> 25 #include <fsl_mmdc.h> 26 #include <spl.h> 27 #include <netdev.h> 28 #include <fsl_sec.h> 29 #include "../common/qixis.h" 30 #include "ls1012aqds_qixis.h" 31 #include "ls1012aqds_pfe.h" 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 int checkboard(void) 36 { 37 char buf[64]; 38 u8 sw; 39 40 sw = QIXIS_READ(arch); 41 printf("Board Arch: V%d, ", sw >> 4); 42 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); 43 44 sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); 45 46 if (sw & QIXIS_LBMAP_ALTBANK) 47 printf("flash: 2\n"); 48 else 49 printf("flash: 1\n"); 50 51 printf("FPGA: v%d (%s), build %d", 52 (int)QIXIS_READ(scver), qixis_read_tag(buf), 53 (int)qixis_read_minor()); 54 55 /* the timestamp string contains "\n" at the end */ 56 printf(" on %s", qixis_read_time(buf)); 57 return 0; 58 } 59 60 int dram_init(void) 61 { 62 static const struct fsl_mmdc_info mparam = { 63 0x05180000, /* mdctl */ 64 0x00030035, /* mdpdc */ 65 0x12554000, /* mdotc */ 66 0xbabf7954, /* mdcfg0 */ 67 0xdb328f64, /* mdcfg1 */ 68 0x01ff00db, /* mdcfg2 */ 69 0x00001680, /* mdmisc */ 70 0x0f3c8000, /* mdref */ 71 0x00002000, /* mdrwd */ 72 0x00bf1023, /* mdor */ 73 0x0000003f, /* mdasp */ 74 0x0000022a, /* mpodtctrl */ 75 0xa1390003, /* mpzqhwctrl */ 76 }; 77 78 mmdc_init(&mparam); 79 80 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 81 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 82 /* This will break-before-make MMU for DDR */ 83 update_early_mmu_table(); 84 #endif 85 86 return 0; 87 } 88 89 int board_early_init_f(void) 90 { 91 fsl_lsch2_early_init_f(); 92 93 return 0; 94 } 95 96 #ifdef CONFIG_MISC_INIT_R 97 int misc_init_r(void) 98 { 99 u8 mux_sdhc_cd = 0x80; 100 101 i2c_set_bus_num(0); 102 103 i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); 104 return 0; 105 } 106 #endif 107 108 int board_init(void) 109 { 110 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + 111 CONFIG_SYS_CCI400_OFFSET); 112 113 /* Set CCI-400 control override register to enable barrier 114 * transaction */ 115 out_le32(&cci->ctrl_ord, 116 CCI400_CTRLORD_EN_BARRIER); 117 118 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 119 erratum_a010315(); 120 #endif 121 122 #ifdef CONFIG_ENV_IS_NOWHERE 123 gd->env_addr = (ulong)&default_environment[0]; 124 #endif 125 126 #ifdef CONFIG_FSL_CAAM 127 sec_init(); 128 #endif 129 130 #ifdef CONFIG_FSL_LS_PPA 131 ppa_init(); 132 #endif 133 return 0; 134 } 135 136 int esdhc_status_fixup(void *blob, const char *compat) 137 { 138 char esdhc0_path[] = "/soc/esdhc@1560000"; 139 char esdhc1_path[] = "/soc/esdhc@1580000"; 140 u8 card_id; 141 142 do_fixup_by_path(blob, esdhc0_path, "status", "okay", 143 sizeof("okay"), 1); 144 145 /* 146 * The Presence Detect 2 register detects the installation 147 * of cards in various PCI Express or SGMII slots. 148 * 149 * STAT_PRS2[7:5]: Specifies the type of card installed in the 150 * SDHC2 Adapter slot. 0b111 indicates no adapter is installed. 151 */ 152 card_id = (QIXIS_READ(present2) & 0xe0) >> 5; 153 154 /* If no adapter is installed in SDHC2, disable SDHC2 */ 155 if (card_id == 0x7) 156 do_fixup_by_path(blob, esdhc1_path, "status", "disabled", 157 sizeof("disabled"), 1); 158 else 159 do_fixup_by_path(blob, esdhc1_path, "status", "okay", 160 sizeof("okay"), 1); 161 return 0; 162 } 163 164 static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val, 165 char *enet_path, char *mdio_path) 166 { 167 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id", 168 &prop_val.busid, PFE_PROP_LEN, 1); 169 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id", 170 &prop_val.phyid, PFE_PROP_LEN, 1); 171 do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val", 172 &prop_val.mux_val, PFE_PROP_LEN, 1); 173 do_fixup_by_path(set_blob, enet_path, "phy-mode", 174 prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1); 175 do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask", 176 &prop_val.phy_mask, PFE_PROP_LEN, 1); 177 return 0; 178 } 179 180 static void fdt_fsl_fixup_of_pfe(void *blob) 181 { 182 int i = 0; 183 struct pfe_prop_val prop_val; 184 void *l_blob = blob; 185 186 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 187 unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) & 188 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; 189 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; 190 191 for (i = 0; i < NUM_ETH_NODE; i++) { 192 switch (srds_s1) { 193 case SERDES_1_G_PROTOCOL: 194 if (i == 0) { 195 prop_val.busid = cpu_to_fdt32( 196 ETH_1_1G_BUS_ID); 197 prop_val.phyid = cpu_to_fdt32( 198 ETH_1_1G_PHY_ID); 199 prop_val.mux_val = cpu_to_fdt32( 200 ETH_1_1G_MDIO_MUX); 201 prop_val.phy_mask = cpu_to_fdt32( 202 ETH_1G_MDIO_PHY_MASK); 203 prop_val.phy_mode = "sgmii"; 204 pfe_set_properties(l_blob, prop_val, ETH_1_PATH, 205 ETH_1_MDIO); 206 } else { 207 prop_val.busid = cpu_to_fdt32( 208 ETH_2_1G_BUS_ID); 209 prop_val.phyid = cpu_to_fdt32( 210 ETH_2_1G_PHY_ID); 211 prop_val.mux_val = cpu_to_fdt32( 212 ETH_2_1G_MDIO_MUX); 213 prop_val.phy_mask = cpu_to_fdt32( 214 ETH_1G_MDIO_PHY_MASK); 215 prop_val.phy_mode = "rgmii"; 216 pfe_set_properties(l_blob, prop_val, ETH_2_PATH, 217 ETH_2_MDIO); 218 } 219 break; 220 case SERDES_2_5_G_PROTOCOL: 221 if (i == 0) { 222 prop_val.busid = cpu_to_fdt32( 223 ETH_1_2_5G_BUS_ID); 224 prop_val.phyid = cpu_to_fdt32( 225 ETH_1_2_5G_PHY_ID); 226 prop_val.mux_val = cpu_to_fdt32( 227 ETH_1_2_5G_MDIO_MUX); 228 prop_val.phy_mask = cpu_to_fdt32( 229 ETH_2_5G_MDIO_PHY_MASK); 230 prop_val.phy_mode = "sgmii-2500"; 231 pfe_set_properties(l_blob, prop_val, ETH_1_PATH, 232 ETH_1_MDIO); 233 } else { 234 prop_val.busid = cpu_to_fdt32( 235 ETH_2_2_5G_BUS_ID); 236 prop_val.phyid = cpu_to_fdt32( 237 ETH_2_2_5G_PHY_ID); 238 prop_val.mux_val = cpu_to_fdt32( 239 ETH_2_2_5G_MDIO_MUX); 240 prop_val.phy_mask = cpu_to_fdt32( 241 ETH_2_5G_MDIO_PHY_MASK); 242 prop_val.phy_mode = "sgmii-2500"; 243 pfe_set_properties(l_blob, prop_val, ETH_2_PATH, 244 ETH_2_MDIO); 245 } 246 break; 247 default: 248 printf("serdes:[%d]\n", srds_s1); 249 } 250 } 251 } 252 253 #ifdef CONFIG_OF_BOARD_SETUP 254 int ft_board_setup(void *blob, bd_t *bd) 255 { 256 arch_fixup_fdt(blob); 257 258 ft_cpu_setup(blob, bd); 259 fdt_fsl_fixup_of_pfe(blob); 260 261 return 0; 262 } 263 #endif 264