1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <fdt_support.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <asm/arch/fdt.h> 14 #include <asm/arch/soc.h> 15 #include <ahci.h> 16 #include <hwconfig.h> 17 #include <mmc.h> 18 #include <scsi.h> 19 #include <fm_eth.h> 20 #include <fsl_esdhc.h> 21 #include <fsl_mmdc.h> 22 #include <spl.h> 23 #include <netdev.h> 24 25 #include "../common/qixis.h" 26 #include "ls1012aqds_qixis.h" 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) 31 { 32 int timeout = 1000; 33 34 out_be32(ptr, value); 35 36 while (in_be32(ptr) & bits) { 37 udelay(100); 38 timeout--; 39 } 40 if (timeout <= 0) 41 puts("Error: wait for clear timeout.\n"); 42 } 43 44 int checkboard(void) 45 { 46 char buf[64]; 47 u8 sw; 48 49 sw = QIXIS_READ(arch); 50 printf("Board Arch: V%d, ", sw >> 4); 51 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); 52 53 sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); 54 55 if (sw & QIXIS_LBMAP_ALTBANK) 56 printf("flash: 2\n"); 57 else 58 printf("flash: 1\n"); 59 60 printf("FPGA: v%d (%s), build %d", 61 (int)QIXIS_READ(scver), qixis_read_tag(buf), 62 (int)qixis_read_minor()); 63 64 /* the timestamp string contains "\n" at the end */ 65 printf(" on %s", qixis_read_time(buf)); 66 return 0; 67 } 68 69 void mmdc_init(void) 70 { 71 struct mmdc_p_regs *mmdc = 72 (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; 73 74 out_be32(&mmdc->mdscr, CONFIGURATION_REQ); 75 76 /* configure timing parms */ 77 out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); 78 out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); 79 out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); 80 out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); 81 82 /* other parms */ 83 out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); 84 out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); 85 out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); 86 out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); 87 88 /* out of reset delays */ 89 out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); 90 91 /* physical parms */ 92 out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); 93 out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); 94 95 /* Enable MMDC */ 96 out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); 97 98 /* dram init sequence: update MRs */ 99 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | 100 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); 101 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 102 CMD_BANK_ADDR_3)); 103 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 104 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); 105 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | 106 CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | 107 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); 108 109 /* dram init sequence: ZQCL */ 110 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | 111 CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); 112 set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 113 CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, 114 FORCE_ZQ_AUTO_CALIBRATION); 115 116 /* Calibrations now: wr lvl */ 117 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | 118 CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 119 CMD_BANK_ADDR_1)); 120 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); 121 set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); 122 123 mdelay(1); 124 125 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 126 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); 127 out_be32(&mmdc->mdscr, CONFIGURATION_REQ); 128 129 mdelay(1); 130 131 /* Calibrations now: Read DQS gating calibration */ 132 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | 133 CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); 134 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 135 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); 136 out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); 137 out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); 138 set_wait_for_bits_clear(&mmdc->mpdgctrl0, 139 AUTO_RD_DQS_GATING_CALIBRATION_EN, 140 AUTO_RD_DQS_GATING_CALIBRATION_EN); 141 142 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 143 CMD_BANK_ADDR_3)); 144 145 /* Calibrations now: Read calibration */ 146 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | 147 CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); 148 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 149 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); 150 out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); 151 set_wait_for_bits_clear(&mmdc->mprddlhwctl, 152 AUTO_RD_CALIBRATION_EN, 153 AUTO_RD_CALIBRATION_EN); 154 155 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 156 CMD_BANK_ADDR_3)); 157 158 /* PD, SR */ 159 out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); 160 out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); 161 162 /* refresh scheme */ 163 set_wait_for_bits_clear(&mmdc->mdref, 164 CONFIG_SYS_MMDC_CORE_REFRESH_CTL, 165 START_REFRESH); 166 167 /* disable CON_REQ */ 168 out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); 169 } 170 171 int dram_init(void) 172 { 173 mmdc_init(); 174 175 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 176 177 return 0; 178 } 179 180 int board_early_init_f(void) 181 { 182 fsl_lsch2_early_init_f(); 183 184 return 0; 185 } 186 187 #ifdef CONFIG_MISC_INIT_R 188 int misc_init_r(void) 189 { 190 u8 mux_sdhc_cd = 0x80; 191 192 i2c_set_bus_num(0); 193 194 i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); 195 return 0; 196 } 197 #endif 198 199 int board_init(void) 200 { 201 struct ccsr_cci400 *cci = (struct ccsr_cci400 *) 202 CONFIG_SYS_CCI400_ADDR; 203 204 /* Set CCI-400 control override register to enable barrier 205 * transaction */ 206 out_le32(&cci->ctrl_ord, 207 CCI400_CTRLORD_EN_BARRIER); 208 209 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 210 erratum_a010315(); 211 #endif 212 213 #ifdef CONFIG_ENV_IS_NOWHERE 214 gd->env_addr = (ulong)&default_environment[0]; 215 #endif 216 return 0; 217 } 218 219 int board_eth_init(bd_t *bis) 220 { 221 return pci_eth_init(bis); 222 } 223 224 #ifdef CONFIG_OF_BOARD_SETUP 225 int ft_board_setup(void *blob, bd_t *bd) 226 { 227 arch_fixup_fdt(blob); 228 229 ft_cpu_setup(blob, bd); 230 231 return 0; 232 } 233 #endif 234