1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "qemu/module.h" 15 #include "qemu/error-report.h" 16 #include "hw/i2c/aspeed_i2c.h" 17 #include "net/net.h" 18 #include "sysemu/sysemu.h" 19 #include "target/arm/cpu-qom.h" 20 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 23 24 static const hwaddr aspeed_soc_ast2600_memmap[] = { 25 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 26 [ASPEED_DEV_SRAM] = 0x10000000, 27 [ASPEED_DEV_DPMCU] = 0x18000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_DEV_IOMEM] = 0x1E600000, 30 [ASPEED_DEV_PWM] = 0x1E610000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_SPI2] = 0x1E631000, 34 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 35 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 36 [ASPEED_DEV_UHCI] = 0x1E6B0000, 37 [ASPEED_DEV_MII1] = 0x1E650000, 38 [ASPEED_DEV_MII2] = 0x1E650008, 39 [ASPEED_DEV_MII3] = 0x1E650010, 40 [ASPEED_DEV_MII4] = 0x1E650018, 41 [ASPEED_DEV_ETH1] = 0x1E660000, 42 [ASPEED_DEV_ETH3] = 0x1E670000, 43 [ASPEED_DEV_ETH2] = 0x1E680000, 44 [ASPEED_DEV_ETH4] = 0x1E690000, 45 [ASPEED_DEV_VIC] = 0x1E6C0000, 46 [ASPEED_DEV_HACE] = 0x1E6D0000, 47 [ASPEED_DEV_SDMC] = 0x1E6E0000, 48 [ASPEED_DEV_SCU] = 0x1E6E2000, 49 [ASPEED_DEV_GFX] = 0x1E6E6000, 50 [ASPEED_DEV_XDMA] = 0x1E6E7000, 51 [ASPEED_DEV_ADC] = 0x1E6E9000, 52 [ASPEED_DEV_DP] = 0x1E6EB000, 53 [ASPEED_DEV_SBC] = 0x1E6F2000, 54 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000, 55 [ASPEED_DEV_VIDEO] = 0x1E700000, 56 [ASPEED_DEV_SDHCI] = 0x1E740000, 57 [ASPEED_DEV_EMMC] = 0x1E750000, 58 [ASPEED_DEV_GPIO] = 0x1E780000, 59 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 60 [ASPEED_DEV_RTC] = 0x1E781000, 61 [ASPEED_DEV_TIMER1] = 0x1E782000, 62 [ASPEED_DEV_WDT] = 0x1E785000, 63 [ASPEED_DEV_LPC] = 0x1E789000, 64 [ASPEED_DEV_IBT] = 0x1E789140, 65 [ASPEED_DEV_I2C] = 0x1E78A000, 66 [ASPEED_DEV_PECI] = 0x1E78B000, 67 [ASPEED_DEV_UART1] = 0x1E783000, 68 [ASPEED_DEV_UART2] = 0x1E78D000, 69 [ASPEED_DEV_UART3] = 0x1E78E000, 70 [ASPEED_DEV_UART4] = 0x1E78F000, 71 [ASPEED_DEV_UART5] = 0x1E784000, 72 [ASPEED_DEV_UART6] = 0x1E790000, 73 [ASPEED_DEV_UART7] = 0x1E790100, 74 [ASPEED_DEV_UART8] = 0x1E790200, 75 [ASPEED_DEV_UART9] = 0x1E790300, 76 [ASPEED_DEV_UART10] = 0x1E790400, 77 [ASPEED_DEV_UART11] = 0x1E790500, 78 [ASPEED_DEV_UART12] = 0x1E790600, 79 [ASPEED_DEV_UART13] = 0x1E790700, 80 [ASPEED_DEV_VUART] = 0x1E787000, 81 [ASPEED_DEV_FSI1] = 0x1E79B000, 82 [ASPEED_DEV_FSI2] = 0x1E79B100, 83 [ASPEED_DEV_I3C] = 0x1E7A0000, 84 [ASPEED_DEV_SDRAM] = 0x80000000, 85 }; 86 87 #define ASPEED_A7MPCORE_ADDR 0x40460000 88 89 #define AST2600_MAX_IRQ 197 90 91 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 92 static const int aspeed_soc_ast2600_irqmap[] = { 93 [ASPEED_DEV_UART1] = 47, 94 [ASPEED_DEV_UART2] = 48, 95 [ASPEED_DEV_UART3] = 49, 96 [ASPEED_DEV_UART4] = 50, 97 [ASPEED_DEV_UART5] = 8, 98 [ASPEED_DEV_UART6] = 57, 99 [ASPEED_DEV_UART7] = 58, 100 [ASPEED_DEV_UART8] = 59, 101 [ASPEED_DEV_UART9] = 60, 102 [ASPEED_DEV_UART10] = 61, 103 [ASPEED_DEV_UART11] = 62, 104 [ASPEED_DEV_UART12] = 63, 105 [ASPEED_DEV_UART13] = 64, 106 [ASPEED_DEV_VUART] = 8, 107 [ASPEED_DEV_FMC] = 39, 108 [ASPEED_DEV_SDMC] = 0, 109 [ASPEED_DEV_SCU] = 12, 110 [ASPEED_DEV_ADC] = 78, 111 [ASPEED_DEV_GFX] = 14, 112 [ASPEED_DEV_XDMA] = 6, 113 [ASPEED_DEV_SDHCI] = 43, 114 [ASPEED_DEV_EHCI1] = 5, 115 [ASPEED_DEV_EHCI2] = 9, 116 [ASPEED_DEV_UHCI] = 10, 117 [ASPEED_DEV_EMMC] = 15, 118 [ASPEED_DEV_GPIO] = 40, 119 [ASPEED_DEV_GPIO_1_8V] = 11, 120 [ASPEED_DEV_RTC] = 13, 121 [ASPEED_DEV_TIMER1] = 16, 122 [ASPEED_DEV_TIMER2] = 17, 123 [ASPEED_DEV_TIMER3] = 18, 124 [ASPEED_DEV_TIMER4] = 19, 125 [ASPEED_DEV_TIMER5] = 20, 126 [ASPEED_DEV_TIMER6] = 21, 127 [ASPEED_DEV_TIMER7] = 22, 128 [ASPEED_DEV_TIMER8] = 23, 129 [ASPEED_DEV_WDT] = 24, 130 [ASPEED_DEV_PWM] = 44, 131 [ASPEED_DEV_LPC] = 35, 132 [ASPEED_DEV_IBT] = 143, 133 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 134 [ASPEED_DEV_PECI] = 38, 135 [ASPEED_DEV_ETH1] = 2, 136 [ASPEED_DEV_ETH2] = 3, 137 [ASPEED_DEV_HACE] = 4, 138 [ASPEED_DEV_ETH3] = 32, 139 [ASPEED_DEV_ETH4] = 33, 140 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 141 [ASPEED_DEV_DP] = 62, 142 [ASPEED_DEV_FSI1] = 100, 143 [ASPEED_DEV_FSI2] = 101, 144 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ 145 }; 146 147 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) 148 { 149 Aspeed2600SoCState *a = ASPEED2600_SOC(s); 150 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 151 152 return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]); 153 } 154 155 static void aspeed_soc_ast2600_init(Object *obj) 156 { 157 Aspeed2600SoCState *a = ASPEED2600_SOC(obj); 158 AspeedSoCState *s = ASPEED_SOC(obj); 159 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 160 int i; 161 char socname[8]; 162 char typename[64]; 163 164 if (sscanf(sc->name, "%7s", socname) != 1) { 165 g_assert_not_reached(); 166 } 167 168 for (i = 0; i < sc->num_cpus; i++) { 169 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 170 aspeed_soc_cpu_type(sc)); 171 } 172 173 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 174 object_initialize_child(obj, "scu", &s->scu, typename); 175 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 176 sc->silicon_rev); 177 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 178 "hw-strap1"); 179 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 180 "hw-strap2"); 181 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 182 "hw-prot-key"); 183 184 object_initialize_child(obj, "a7mpcore", &a->a7mpcore, 185 TYPE_A15MPCORE_PRIV); 186 187 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 188 189 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 190 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 191 192 for (i = 0; i < sc->wdts_num; i++) { 193 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 194 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 195 } 196 197 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 198 object_initialize_child(obj, "adc", &s->adc, typename); 199 200 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 201 object_initialize_child(obj, "i2c", &s->i2c, typename); 202 203 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 204 205 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 206 object_initialize_child(obj, "fmc", &s->fmc, typename); 207 208 for (i = 0; i < sc->spis_num; i++) { 209 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 210 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 211 } 212 213 for (i = 0; i < sc->ehcis_num; i++) { 214 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 215 TYPE_PLATFORM_EHCI); 216 } 217 218 object_initialize_child(obj, "uhci", &s->uhci, TYPE_ASPEED_UHCI); 219 220 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 221 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 222 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 223 "ram-size"); 224 225 for (i = 0; i < sc->macs_num; i++) { 226 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 227 TYPE_FTGMAC100); 228 229 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 230 } 231 232 for (i = 0; i < sc->uarts_num; i++) { 233 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 234 } 235 236 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 237 object_initialize_child(obj, "xdma", &s->xdma, typename); 238 239 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 240 object_initialize_child(obj, "gpio", &s->gpio, typename); 241 242 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 243 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 244 245 object_initialize_child(obj, "sd-controller", &s->sdhci, 246 TYPE_ASPEED_SDHCI); 247 248 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 249 250 /* Init sd card slot class here so that they're under the correct parent */ 251 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 252 object_initialize_child(obj, "sd-controller.sdhci[*]", 253 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 254 } 255 256 object_initialize_child(obj, "emmc-controller", &s->emmc, 257 TYPE_ASPEED_SDHCI); 258 259 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 260 261 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 262 TYPE_SYSBUS_SDHCI); 263 264 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 265 266 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 267 object_initialize_child(obj, "hace", &s->hace, typename); 268 269 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 270 271 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); 272 273 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 274 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 275 object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); 276 object_initialize_child(obj, "emmc-boot-controller", 277 &s->emmc_boot_controller, 278 TYPE_UNIMPLEMENTED_DEVICE); 279 280 for (i = 0; i < ASPEED_FSI_NUM; i++) { 281 object_initialize_child(obj, "fsi[*]", &s->fsi[i], TYPE_ASPEED_APB2OPB); 282 } 283 284 object_initialize_child(obj, "gfx", &s->gfx, TYPE_ASPEED_GFX); 285 286 object_initialize_child(obj, "pwm", &s->pwm, TYPE_ASPEED_PWM); 287 } 288 289 /* 290 * ASPEED ast2600 has 0xf as cluster ID 291 * 292 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 293 */ 294 static uint64_t aspeed_calc_affinity(int cpu) 295 { 296 return (0xf << ARM_AFF1_SHIFT) | cpu; 297 } 298 299 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 300 { 301 int i; 302 Aspeed2600SoCState *a = ASPEED2600_SOC(dev); 303 AspeedSoCState *s = ASPEED_SOC(dev); 304 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 305 qemu_irq irq; 306 g_autofree char *sram_name = NULL; 307 g_autofree char *usb_bus = g_strdup_printf("usb-bus.%u", sc->ehcis_num - 1); 308 309 /* Default boot region (SPI memory or ROMs) */ 310 memory_region_init(&s->spi_boot_container, OBJECT(s), 311 "aspeed.spi_boot_container", 0x10000000); 312 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 313 &s->spi_boot_container); 314 315 /* IO space */ 316 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 317 sc->memmap[ASPEED_DEV_IOMEM], 318 ASPEED_SOC_IOMEM_SIZE); 319 320 /* Video engine stub */ 321 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 322 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 323 324 /* eMMC Boot Controller stub */ 325 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller), 326 "aspeed.emmc-boot-controller", 327 sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000); 328 329 /* CPU */ 330 for (i = 0; i < sc->num_cpus; i++) { 331 if (sc->num_cpus > 1) { 332 object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar", 333 ASPEED_A7MPCORE_ADDR, &error_abort); 334 } 335 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 336 aspeed_calc_affinity(i), &error_abort); 337 338 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 339 &error_abort); 340 object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false, 341 &error_abort); 342 object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false, 343 &error_abort); 344 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 345 OBJECT(s->memory), &error_abort); 346 347 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 348 return; 349 } 350 } 351 352 /* A7MPCORE */ 353 object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus, 354 &error_abort); 355 object_property_set_int(OBJECT(&a->a7mpcore), "num-irq", 356 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 357 &error_abort); 358 359 sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort); 360 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 361 362 for (i = 0; i < sc->num_cpus; i++) { 363 SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore); 364 DeviceState *d = DEVICE(&a->cpu[i]); 365 366 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 367 sysbus_connect_irq(sbd, i, irq); 368 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 369 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 370 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 371 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 372 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 373 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 374 } 375 376 /* SRAM */ 377 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 378 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 379 errp)) { 380 return; 381 } 382 memory_region_add_subregion(s->memory, 383 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 384 385 /* DPMCU */ 386 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", 387 sc->memmap[ASPEED_DEV_DPMCU], 388 ASPEED_SOC_DPMCU_SIZE); 389 390 /* SCU */ 391 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 392 return; 393 } 394 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 395 396 /* RTC */ 397 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 398 return; 399 } 400 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 401 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 402 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 403 404 /* Timer */ 405 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 406 &error_abort); 407 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 408 return; 409 } 410 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 411 sc->memmap[ASPEED_DEV_TIMER1]); 412 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 413 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 414 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 415 } 416 417 /* Watch dog */ 418 for (i = 0; i < sc->wdts_num; i++) { 419 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 420 421 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 422 &error_abort); 423 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 424 return; 425 } 426 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, 427 sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize); 428 } 429 430 /* ADC */ 431 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 432 return; 433 } 434 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 435 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 436 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 437 438 /* UART */ 439 if (!aspeed_soc_uart_realize(s, errp)) { 440 return; 441 } 442 443 /* I2C */ 444 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 445 &error_abort); 446 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 447 return; 448 } 449 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 450 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 451 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 452 sc->irqmap[ASPEED_DEV_I2C] + i); 453 /* The AST2600 I2C controller has one IRQ per bus. */ 454 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 455 } 456 457 /* PECI */ 458 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 459 return; 460 } 461 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 462 sc->memmap[ASPEED_DEV_PECI]); 463 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 464 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 465 466 /* FMC, The number of CS is set at the board level */ 467 object_property_set_link(OBJECT(&s->fmc), "wdt2", OBJECT(&s->wdt[2].iomem), 468 &error_abort); 469 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 470 &error_abort); 471 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 472 return; 473 } 474 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 475 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 476 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 477 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 478 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 479 480 /* Set up an alias on the FMC CE0 region (boot default) */ 481 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 482 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 483 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 484 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 485 486 /* SPI */ 487 for (i = 0; i < sc->spis_num; i++) { 488 object_property_set_link(OBJECT(&s->spi[i]), "dram", 489 OBJECT(s->dram_mr), &error_abort); 490 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 491 return; 492 } 493 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 494 sc->memmap[ASPEED_DEV_SPI1 + i]); 495 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 496 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 497 } 498 499 /* EHCI */ 500 for (i = 0; i < sc->ehcis_num; i++) { 501 if (i == sc->ehcis_num - 1) { 502 object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", 503 true, &error_fatal); 504 } 505 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 506 return; 507 } 508 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 509 sc->memmap[ASPEED_DEV_EHCI1 + i]); 510 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 511 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 512 } 513 514 /* UHCI */ 515 object_property_set_str(OBJECT(&s->uhci), "masterbus", usb_bus, 516 &error_fatal); 517 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uhci), errp)) { 518 return; 519 } 520 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->uhci), 0, 521 sc->memmap[ASPEED_DEV_UHCI]); 522 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uhci), 0, 523 aspeed_soc_get_irq(s, ASPEED_DEV_UHCI)); 524 525 /* SDMC - SDRAM Memory Controller */ 526 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 527 return; 528 } 529 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 530 sc->memmap[ASPEED_DEV_SDMC]); 531 532 /* RAM */ 533 if (!aspeed_soc_dram_init(s, errp)) { 534 return; 535 } 536 537 /* Net */ 538 for (i = 0; i < sc->macs_num; i++) { 539 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 540 &error_abort); 541 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 542 return; 543 } 544 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 545 sc->memmap[ASPEED_DEV_ETH1 + i]); 546 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 547 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 548 549 object_property_set_link(OBJECT(&s->mii[i]), "nic", 550 OBJECT(&s->ftgmac100[i]), &error_abort); 551 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 552 return; 553 } 554 555 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 556 sc->memmap[ASPEED_DEV_MII1 + i]); 557 } 558 559 /* XDMA */ 560 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 561 return; 562 } 563 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 564 sc->memmap[ASPEED_DEV_XDMA]); 565 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 566 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 567 568 /* GPIO */ 569 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 570 return; 571 } 572 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 573 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 574 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 575 576 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 577 return; 578 } 579 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 580 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 581 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 582 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 583 584 /* SDHCI */ 585 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 586 return; 587 } 588 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 589 sc->memmap[ASPEED_DEV_SDHCI]); 590 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 591 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 592 593 /* eMMC */ 594 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 595 return; 596 } 597 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 598 sc->memmap[ASPEED_DEV_EMMC]); 599 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 600 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 601 602 /* LPC */ 603 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 604 return; 605 } 606 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 607 608 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 609 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 610 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 611 612 /* 613 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 614 * 615 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 616 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 617 * shared across the subdevices, and the shared IRQ output to the VIC is at 618 * offset 0. 619 */ 620 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 621 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 622 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 623 624 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 625 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 626 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 627 628 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 629 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 630 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 631 632 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 633 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 634 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 635 636 /* HACE */ 637 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 638 &error_abort); 639 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 640 return; 641 } 642 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 643 sc->memmap[ASPEED_DEV_HACE]); 644 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 645 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 646 647 /* I3C */ 648 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 649 return; 650 } 651 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 652 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 653 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 654 sc->irqmap[ASPEED_DEV_I3C] + i); 655 /* The AST2600 I3C controller has one IRQ per bus. */ 656 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 657 } 658 659 /* Secure Boot Controller */ 660 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 661 return; 662 } 663 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 664 665 /* FSI */ 666 for (i = 0; i < ASPEED_FSI_NUM; i++) { 667 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[i]), errp)) { 668 return; 669 } 670 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fsi[i]), 0, 671 sc->memmap[ASPEED_DEV_FSI1 + i]); 672 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[i]), 0, 673 aspeed_soc_get_irq(s, ASPEED_DEV_FSI1 + i)); 674 } 675 676 /* GFX */ 677 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gfx), errp)) { 678 return; 679 } 680 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gfx), 0, sc->memmap[ASPEED_DEV_GFX]); 681 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gfx), 0, 682 aspeed_soc_get_irq(s, ASPEED_DEV_GFX)); 683 684 /* PWM */ 685 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp)) { 686 return; 687 } 688 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pwm), 0, sc->memmap[ASPEED_DEV_PWM]); 689 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm), 0, 690 aspeed_soc_get_irq(s, ASPEED_DEV_PWM)); 691 } 692 693 static bool aspeed_soc_ast2600_boot_from_emmc(AspeedSoCState *s) 694 { 695 uint32_t hw_strap1 = object_property_get_uint(OBJECT(&s->scu), 696 "hw-strap1", &error_abort); 697 return !!(hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 698 } 699 700 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 701 { 702 static const char * const valid_cpu_types[] = { 703 ARM_CPU_TYPE_NAME("cortex-a7"), 704 NULL 705 }; 706 DeviceClass *dc = DEVICE_CLASS(oc); 707 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 708 709 dc->realize = aspeed_soc_ast2600_realize; 710 /* Reason: The Aspeed SoC can only be instantiated from a board */ 711 dc->user_creatable = false; 712 713 sc->name = "ast2600-a3"; 714 sc->valid_cpu_types = valid_cpu_types; 715 sc->silicon_rev = AST2600_A3_SILICON_REV; 716 sc->sram_size = 0x16400; 717 sc->spis_num = 2; 718 sc->ehcis_num = 2; 719 sc->wdts_num = 4; 720 sc->macs_num = 4; 721 sc->uarts_num = 13; 722 sc->uarts_base = ASPEED_DEV_UART1; 723 sc->irqmap = aspeed_soc_ast2600_irqmap; 724 sc->memmap = aspeed_soc_ast2600_memmap; 725 sc->num_cpus = 2; 726 sc->get_irq = aspeed_soc_ast2600_get_irq; 727 sc->boot_from_emmc = aspeed_soc_ast2600_boot_from_emmc; 728 } 729 730 static const TypeInfo aspeed_soc_ast2600_types[] = { 731 { 732 .name = TYPE_ASPEED2600_SOC, 733 .parent = TYPE_ASPEED_SOC, 734 .instance_size = sizeof(Aspeed2600SoCState), 735 .abstract = true, 736 }, { 737 .name = "ast2600-a3", 738 .parent = TYPE_ASPEED2600_SOC, 739 .instance_init = aspeed_soc_ast2600_init, 740 .class_init = aspeed_soc_ast2600_class_init, 741 }, 742 }; 743 744 DEFINE_TYPES(aspeed_soc_ast2600_types) 745