1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "qemu/module.h" 15 #include "qemu/error-report.h" 16 #include "hw/i2c/aspeed_i2c.h" 17 #include "net/net.h" 18 #include "sysemu/sysemu.h" 19 #include "target/arm/cpu-qom.h" 20 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 23 24 static const hwaddr aspeed_soc_ast2600_memmap[] = { 25 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 26 [ASPEED_DEV_SRAM] = 0x10000000, 27 [ASPEED_DEV_DPMCU] = 0x18000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_DEV_IOMEM] = 0x1E600000, 30 [ASPEED_DEV_PWM] = 0x1E610000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_SPI2] = 0x1E631000, 34 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 35 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 36 [ASPEED_DEV_UHCI] = 0x1E6B0000, 37 [ASPEED_DEV_MII1] = 0x1E650000, 38 [ASPEED_DEV_MII2] = 0x1E650008, 39 [ASPEED_DEV_MII3] = 0x1E650010, 40 [ASPEED_DEV_MII4] = 0x1E650018, 41 [ASPEED_DEV_ETH1] = 0x1E660000, 42 [ASPEED_DEV_ETH3] = 0x1E670000, 43 [ASPEED_DEV_ETH2] = 0x1E680000, 44 [ASPEED_DEV_ETH4] = 0x1E690000, 45 [ASPEED_DEV_VIC] = 0x1E6C0000, 46 [ASPEED_DEV_HACE] = 0x1E6D0000, 47 [ASPEED_DEV_SDMC] = 0x1E6E0000, 48 [ASPEED_DEV_SCU] = 0x1E6E2000, 49 [ASPEED_DEV_GFX] = 0x1E6E6000, 50 [ASPEED_DEV_XDMA] = 0x1E6E7000, 51 [ASPEED_DEV_ADC] = 0x1E6E9000, 52 [ASPEED_DEV_DP] = 0x1E6EB000, 53 [ASPEED_DEV_SBC] = 0x1E6F2000, 54 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000, 55 [ASPEED_DEV_VIDEO] = 0x1E700000, 56 [ASPEED_DEV_SDHCI] = 0x1E740000, 57 [ASPEED_DEV_EMMC] = 0x1E750000, 58 [ASPEED_DEV_GPIO] = 0x1E780000, 59 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 60 [ASPEED_DEV_RTC] = 0x1E781000, 61 [ASPEED_DEV_TIMER1] = 0x1E782000, 62 [ASPEED_DEV_WDT] = 0x1E785000, 63 [ASPEED_DEV_LPC] = 0x1E789000, 64 [ASPEED_DEV_IBT] = 0x1E789140, 65 [ASPEED_DEV_I2C] = 0x1E78A000, 66 [ASPEED_DEV_PECI] = 0x1E78B000, 67 [ASPEED_DEV_UART1] = 0x1E783000, 68 [ASPEED_DEV_UART2] = 0x1E78D000, 69 [ASPEED_DEV_UART3] = 0x1E78E000, 70 [ASPEED_DEV_UART4] = 0x1E78F000, 71 [ASPEED_DEV_UART5] = 0x1E784000, 72 [ASPEED_DEV_UART6] = 0x1E790000, 73 [ASPEED_DEV_UART7] = 0x1E790100, 74 [ASPEED_DEV_UART8] = 0x1E790200, 75 [ASPEED_DEV_UART9] = 0x1E790300, 76 [ASPEED_DEV_UART10] = 0x1E790400, 77 [ASPEED_DEV_UART11] = 0x1E790500, 78 [ASPEED_DEV_UART12] = 0x1E790600, 79 [ASPEED_DEV_UART13] = 0x1E790700, 80 [ASPEED_DEV_VUART] = 0x1E787000, 81 [ASPEED_DEV_FSI1] = 0x1E79B000, 82 [ASPEED_DEV_FSI2] = 0x1E79B100, 83 [ASPEED_DEV_I3C] = 0x1E7A0000, 84 [ASPEED_DEV_SDRAM] = 0x80000000, 85 }; 86 87 #define ASPEED_A7MPCORE_ADDR 0x40460000 88 89 #define AST2600_MAX_IRQ 197 90 91 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 92 static const int aspeed_soc_ast2600_irqmap[] = { 93 [ASPEED_DEV_UART1] = 47, 94 [ASPEED_DEV_UART2] = 48, 95 [ASPEED_DEV_UART3] = 49, 96 [ASPEED_DEV_UART4] = 50, 97 [ASPEED_DEV_UART5] = 8, 98 [ASPEED_DEV_UART6] = 57, 99 [ASPEED_DEV_UART7] = 58, 100 [ASPEED_DEV_UART8] = 59, 101 [ASPEED_DEV_UART9] = 60, 102 [ASPEED_DEV_UART10] = 61, 103 [ASPEED_DEV_UART11] = 62, 104 [ASPEED_DEV_UART12] = 63, 105 [ASPEED_DEV_UART13] = 64, 106 [ASPEED_DEV_VUART] = 8, 107 [ASPEED_DEV_FMC] = 39, 108 [ASPEED_DEV_SDMC] = 0, 109 [ASPEED_DEV_SCU] = 12, 110 [ASPEED_DEV_ADC] = 78, 111 [ASPEED_DEV_GFX] = 14, 112 [ASPEED_DEV_XDMA] = 6, 113 [ASPEED_DEV_SDHCI] = 43, 114 [ASPEED_DEV_EHCI1] = 5, 115 [ASPEED_DEV_EHCI2] = 9, 116 [ASPEED_DEV_UHCI] = 10, 117 [ASPEED_DEV_EMMC] = 15, 118 [ASPEED_DEV_GPIO] = 40, 119 [ASPEED_DEV_GPIO_1_8V] = 11, 120 [ASPEED_DEV_RTC] = 13, 121 [ASPEED_DEV_TIMER1] = 16, 122 [ASPEED_DEV_TIMER2] = 17, 123 [ASPEED_DEV_TIMER3] = 18, 124 [ASPEED_DEV_TIMER4] = 19, 125 [ASPEED_DEV_TIMER5] = 20, 126 [ASPEED_DEV_TIMER6] = 21, 127 [ASPEED_DEV_TIMER7] = 22, 128 [ASPEED_DEV_TIMER8] = 23, 129 [ASPEED_DEV_WDT] = 24, 130 [ASPEED_DEV_PWM] = 44, 131 [ASPEED_DEV_LPC] = 35, 132 [ASPEED_DEV_IBT] = 143, 133 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 134 [ASPEED_DEV_PECI] = 38, 135 [ASPEED_DEV_ETH1] = 2, 136 [ASPEED_DEV_ETH2] = 3, 137 [ASPEED_DEV_HACE] = 4, 138 [ASPEED_DEV_ETH3] = 32, 139 [ASPEED_DEV_ETH4] = 33, 140 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 141 [ASPEED_DEV_DP] = 62, 142 [ASPEED_DEV_FSI1] = 100, 143 [ASPEED_DEV_FSI2] = 101, 144 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ 145 }; 146 147 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) 148 { 149 Aspeed2600SoCState *a = ASPEED2600_SOC(s); 150 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 151 152 return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]); 153 } 154 155 static void aspeed_soc_ast2600_init(Object *obj) 156 { 157 Aspeed2600SoCState *a = ASPEED2600_SOC(obj); 158 AspeedSoCState *s = ASPEED_SOC(obj); 159 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 160 int i; 161 char socname[8]; 162 char typename[64]; 163 164 if (sscanf(sc->name, "%7s", socname) != 1) { 165 g_assert_not_reached(); 166 } 167 168 for (i = 0; i < sc->num_cpus; i++) { 169 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 170 aspeed_soc_cpu_type(sc)); 171 } 172 173 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 174 object_initialize_child(obj, "scu", &s->scu, typename); 175 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 176 sc->silicon_rev); 177 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 178 "hw-strap1"); 179 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 180 "hw-strap2"); 181 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 182 "hw-prot-key"); 183 184 object_initialize_child(obj, "a7mpcore", &a->a7mpcore, 185 TYPE_A15MPCORE_PRIV); 186 187 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 188 189 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 190 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 191 192 for (i = 0; i < sc->wdts_num; i++) { 193 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 194 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 195 } 196 197 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 198 object_initialize_child(obj, "adc", &s->adc, typename); 199 200 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 201 object_initialize_child(obj, "i2c", &s->i2c, typename); 202 203 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 204 205 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 206 object_initialize_child(obj, "fmc", &s->fmc, typename); 207 208 for (i = 0; i < sc->spis_num; i++) { 209 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 210 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 211 } 212 213 for (i = 0; i < sc->ehcis_num; i++) { 214 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 215 TYPE_PLATFORM_EHCI); 216 } 217 218 object_initialize_child(obj, "uhci", &s->uhci, TYPE_ASPEED_UHCI); 219 220 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 221 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 222 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 223 "ram-size"); 224 225 for (i = 0; i < sc->macs_num; i++) { 226 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 227 TYPE_FTGMAC100); 228 229 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 230 } 231 232 for (i = 0; i < sc->uarts_num; i++) { 233 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 234 } 235 236 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 237 object_initialize_child(obj, "xdma", &s->xdma, typename); 238 239 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 240 object_initialize_child(obj, "gpio", &s->gpio, typename); 241 242 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 243 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 244 245 object_initialize_child(obj, "sd-controller", &s->sdhci, 246 TYPE_ASPEED_SDHCI); 247 248 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 249 250 /* Init sd card slot class here so that they're under the correct parent */ 251 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 252 object_initialize_child(obj, "sd-controller.sdhci[*]", 253 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 254 } 255 256 object_initialize_child(obj, "emmc-controller", &s->emmc, 257 TYPE_ASPEED_SDHCI); 258 259 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 260 261 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 262 TYPE_SYSBUS_SDHCI); 263 264 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 265 266 object_initialize_child(obj, "ibt", &s->ibt, TYPE_ASPEED_IBT); 267 268 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 269 object_initialize_child(obj, "hace", &s->hace, typename); 270 271 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 272 273 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); 274 275 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 276 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 277 object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); 278 object_initialize_child(obj, "emmc-boot-controller", 279 &s->emmc_boot_controller, 280 TYPE_UNIMPLEMENTED_DEVICE); 281 282 for (i = 0; i < ASPEED_FSI_NUM; i++) { 283 object_initialize_child(obj, "fsi[*]", &s->fsi[i], TYPE_ASPEED_APB2OPB); 284 } 285 286 object_initialize_child(obj, "gfx", &s->gfx, TYPE_ASPEED_GFX); 287 288 object_initialize_child(obj, "pwm", &s->pwm, TYPE_ASPEED_PWM); 289 } 290 291 /* 292 * ASPEED ast2600 has 0xf as cluster ID 293 * 294 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 295 */ 296 static uint64_t aspeed_calc_affinity(int cpu) 297 { 298 return (0xf << ARM_AFF1_SHIFT) | cpu; 299 } 300 301 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 302 { 303 int i; 304 Aspeed2600SoCState *a = ASPEED2600_SOC(dev); 305 AspeedSoCState *s = ASPEED_SOC(dev); 306 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 307 qemu_irq irq; 308 g_autofree char *sram_name = NULL; 309 g_autofree char *usb_bus = g_strdup_printf("usb-bus.%u", sc->ehcis_num - 1); 310 311 /* Default boot region (SPI memory or ROMs) */ 312 memory_region_init(&s->spi_boot_container, OBJECT(s), 313 "aspeed.spi_boot_container", 0x10000000); 314 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 315 &s->spi_boot_container); 316 317 /* IO space */ 318 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 319 sc->memmap[ASPEED_DEV_IOMEM], 320 ASPEED_SOC_IOMEM_SIZE); 321 322 /* Video engine stub */ 323 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 324 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 325 326 /* eMMC Boot Controller stub */ 327 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller), 328 "aspeed.emmc-boot-controller", 329 sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000); 330 331 /* CPU */ 332 for (i = 0; i < sc->num_cpus; i++) { 333 if (sc->num_cpus > 1) { 334 object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar", 335 ASPEED_A7MPCORE_ADDR, &error_abort); 336 } 337 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 338 aspeed_calc_affinity(i), &error_abort); 339 340 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 341 &error_abort); 342 object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false, 343 &error_abort); 344 object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false, 345 &error_abort); 346 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 347 OBJECT(s->memory), &error_abort); 348 349 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 350 return; 351 } 352 } 353 354 /* A7MPCORE */ 355 object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus, 356 &error_abort); 357 object_property_set_int(OBJECT(&a->a7mpcore), "num-irq", 358 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 359 &error_abort); 360 361 sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort); 362 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 363 364 for (i = 0; i < sc->num_cpus; i++) { 365 SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore); 366 DeviceState *d = DEVICE(&a->cpu[i]); 367 368 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 369 sysbus_connect_irq(sbd, i, irq); 370 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 371 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 372 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 373 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 374 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 375 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 376 } 377 378 /* SRAM */ 379 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 380 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 381 errp)) { 382 return; 383 } 384 memory_region_add_subregion(s->memory, 385 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 386 387 /* DPMCU */ 388 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", 389 sc->memmap[ASPEED_DEV_DPMCU], 390 ASPEED_SOC_DPMCU_SIZE); 391 392 /* SCU */ 393 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 394 return; 395 } 396 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 397 398 /* RTC */ 399 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 400 return; 401 } 402 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 403 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 404 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 405 406 /* Timer */ 407 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 408 &error_abort); 409 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 410 return; 411 } 412 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 413 sc->memmap[ASPEED_DEV_TIMER1]); 414 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 415 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 416 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 417 } 418 419 /* Watch dog */ 420 for (i = 0; i < sc->wdts_num; i++) { 421 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 422 423 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 424 &error_abort); 425 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 426 return; 427 } 428 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, 429 sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize); 430 } 431 432 /* ADC */ 433 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 434 return; 435 } 436 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 437 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 438 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 439 440 /* UART */ 441 if (!aspeed_soc_uart_realize(s, errp)) { 442 return; 443 } 444 445 /* I2C */ 446 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 447 &error_abort); 448 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 449 return; 450 } 451 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 452 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 453 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 454 sc->irqmap[ASPEED_DEV_I2C] + i); 455 /* The AST2600 I2C controller has one IRQ per bus. */ 456 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 457 } 458 459 /* PECI */ 460 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 461 return; 462 } 463 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 464 sc->memmap[ASPEED_DEV_PECI]); 465 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 466 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 467 468 /* FMC, The number of CS is set at the board level */ 469 object_property_set_link(OBJECT(&s->fmc), "wdt2", OBJECT(&s->wdt[2].iomem), 470 &error_abort); 471 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 472 &error_abort); 473 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 474 return; 475 } 476 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 477 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 478 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 479 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 480 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 481 482 /* Set up an alias on the FMC CE0 region (boot default) */ 483 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 484 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 485 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 486 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 487 488 /* SPI */ 489 for (i = 0; i < sc->spis_num; i++) { 490 object_property_set_link(OBJECT(&s->spi[i]), "dram", 491 OBJECT(s->dram_mr), &error_abort); 492 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 493 return; 494 } 495 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 496 sc->memmap[ASPEED_DEV_SPI1 + i]); 497 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 498 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 499 } 500 501 /* EHCI */ 502 for (i = 0; i < sc->ehcis_num; i++) { 503 if (i == sc->ehcis_num - 1) { 504 object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", 505 true, &error_fatal); 506 } 507 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 508 return; 509 } 510 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 511 sc->memmap[ASPEED_DEV_EHCI1 + i]); 512 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 513 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 514 } 515 516 /* UHCI */ 517 object_property_set_str(OBJECT(&s->uhci), "masterbus", usb_bus, 518 &error_fatal); 519 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uhci), errp)) { 520 return; 521 } 522 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->uhci), 0, 523 sc->memmap[ASPEED_DEV_UHCI]); 524 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uhci), 0, 525 aspeed_soc_get_irq(s, ASPEED_DEV_UHCI)); 526 527 /* SDMC - SDRAM Memory Controller */ 528 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 529 return; 530 } 531 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 532 sc->memmap[ASPEED_DEV_SDMC]); 533 534 /* RAM */ 535 if (!aspeed_soc_dram_init(s, errp)) { 536 return; 537 } 538 539 /* Net */ 540 for (i = 0; i < sc->macs_num; i++) { 541 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 542 &error_abort); 543 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 544 return; 545 } 546 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 547 sc->memmap[ASPEED_DEV_ETH1 + i]); 548 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 549 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 550 551 object_property_set_link(OBJECT(&s->mii[i]), "nic", 552 OBJECT(&s->ftgmac100[i]), &error_abort); 553 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 554 return; 555 } 556 557 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 558 sc->memmap[ASPEED_DEV_MII1 + i]); 559 } 560 561 /* XDMA */ 562 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 563 return; 564 } 565 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 566 sc->memmap[ASPEED_DEV_XDMA]); 567 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 568 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 569 570 /* GPIO */ 571 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 572 return; 573 } 574 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 575 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 576 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 577 578 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 579 return; 580 } 581 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 582 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 583 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 584 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 585 586 /* SDHCI */ 587 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 588 return; 589 } 590 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 591 sc->memmap[ASPEED_DEV_SDHCI]); 592 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 593 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 594 595 /* eMMC */ 596 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 597 return; 598 } 599 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 600 sc->memmap[ASPEED_DEV_EMMC]); 601 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 602 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 603 604 /* LPC */ 605 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 606 return; 607 } 608 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 609 610 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 611 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 612 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 613 614 /* 615 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 616 * 617 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 618 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 619 * shared across the subdevices, and the shared IRQ output to the VIC is at 620 * offset 0. 621 */ 622 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 623 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 624 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 625 626 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 627 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 628 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 629 630 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 631 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 632 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 633 634 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 635 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 636 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 637 638 /* iBT */ 639 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ibt), errp)) { 640 return; 641 } 642 memory_region_add_subregion(&s->lpc.iomem, 643 sc->memmap[ASPEED_DEV_IBT] - sc->memmap[ASPEED_DEV_LPC], 644 &s->ibt.iomem); 645 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ibt), 0, 646 aspeed_soc_get_irq(s, ASPEED_DEV_IBT)); 647 648 /* HACE */ 649 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 650 &error_abort); 651 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 652 return; 653 } 654 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 655 sc->memmap[ASPEED_DEV_HACE]); 656 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 657 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 658 659 /* I3C */ 660 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 661 return; 662 } 663 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 664 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 665 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 666 sc->irqmap[ASPEED_DEV_I3C] + i); 667 /* The AST2600 I3C controller has one IRQ per bus. */ 668 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 669 } 670 671 /* Secure Boot Controller */ 672 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 673 return; 674 } 675 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 676 677 /* FSI */ 678 for (i = 0; i < ASPEED_FSI_NUM; i++) { 679 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[i]), errp)) { 680 return; 681 } 682 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fsi[i]), 0, 683 sc->memmap[ASPEED_DEV_FSI1 + i]); 684 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[i]), 0, 685 aspeed_soc_get_irq(s, ASPEED_DEV_FSI1 + i)); 686 } 687 688 /* GFX */ 689 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gfx), errp)) { 690 return; 691 } 692 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gfx), 0, sc->memmap[ASPEED_DEV_GFX]); 693 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gfx), 0, 694 aspeed_soc_get_irq(s, ASPEED_DEV_GFX)); 695 696 /* PWM */ 697 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp)) { 698 return; 699 } 700 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pwm), 0, sc->memmap[ASPEED_DEV_PWM]); 701 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm), 0, 702 aspeed_soc_get_irq(s, ASPEED_DEV_PWM)); 703 } 704 705 static bool aspeed_soc_ast2600_boot_from_emmc(AspeedSoCState *s) 706 { 707 uint32_t hw_strap1 = object_property_get_uint(OBJECT(&s->scu), 708 "hw-strap1", &error_abort); 709 return !!(hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 710 } 711 712 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 713 { 714 static const char * const valid_cpu_types[] = { 715 ARM_CPU_TYPE_NAME("cortex-a7"), 716 NULL 717 }; 718 DeviceClass *dc = DEVICE_CLASS(oc); 719 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 720 721 dc->realize = aspeed_soc_ast2600_realize; 722 /* Reason: The Aspeed SoC can only be instantiated from a board */ 723 dc->user_creatable = false; 724 725 sc->name = "ast2600-a3"; 726 sc->valid_cpu_types = valid_cpu_types; 727 sc->silicon_rev = AST2600_A3_SILICON_REV; 728 sc->sram_size = 0x16400; 729 sc->spis_num = 2; 730 sc->ehcis_num = 2; 731 sc->wdts_num = 4; 732 sc->macs_num = 4; 733 sc->uarts_num = 13; 734 sc->uarts_base = ASPEED_DEV_UART1; 735 sc->irqmap = aspeed_soc_ast2600_irqmap; 736 sc->memmap = aspeed_soc_ast2600_memmap; 737 sc->num_cpus = 2; 738 sc->get_irq = aspeed_soc_ast2600_get_irq; 739 sc->boot_from_emmc = aspeed_soc_ast2600_boot_from_emmc; 740 } 741 742 static const TypeInfo aspeed_soc_ast2600_types[] = { 743 { 744 .name = TYPE_ASPEED2600_SOC, 745 .parent = TYPE_ASPEED_SOC, 746 .instance_size = sizeof(Aspeed2600SoCState), 747 .abstract = true, 748 }, { 749 .name = "ast2600-a3", 750 .parent = TYPE_ASPEED2600_SOC, 751 .instance_init = aspeed_soc_ast2600_init, 752 .class_init = aspeed_soc_ast2600_class_init, 753 }, 754 }; 755 756 DEFINE_TYPES(aspeed_soc_ast2600_types) 757