util: Add RISC-V vector extension probe in cpuinfoAdd support for probing RISC-V vector extension availability inthe backend. This information will be used when deciding whetherto use vector inst
util: Add RISC-V vector extension probe in cpuinfoAdd support for probing RISC-V vector extension availability inthe backend. This information will be used when deciding whetherto use vector instructions in code generation.Cache lg2(vlenb) for the backend. The storing of lg2(vlenb) meanswe can convert all of the division into subtraction.While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X,we use RISCV_HWPROBE_IMA_V instead. RISCV_HWPROBE_IMA_V is morestrictly constrainted than RISCV_HWPROBE_EXT_ZVE64X. At least incurrent QEMU implemenation, the V vector extension depends on thezve64d extension.Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>Message-ID: <20241007025700.47259-2-zhiwei_liu@linux.alibaba.com>Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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util/cpuinfo-riscv: Support host/cpuinfo.h for riscvMove detection code out of tcg, similar to other hosts.Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>Reviewed-by: Alistair Francis <al
util/cpuinfo-riscv: Support host/cpuinfo.h for riscvMove detection code out of tcg, similar to other hosts.Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>Reviewed-by: Alistair Francis <alistair.francis@wdc.com>Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>Signed-off-by: Richard Henderson <richard.henderson@linaro.org>