/openbmc/linux/drivers/phy/mediatek/ |
H A D | phy-mtk-hdmi-mt2701.c | 56 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); in mtk_hdmi_pll_prepare() 84 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN); in mtk_hdmi_pll_unprepare() 86 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); in mtk_hdmi_pll_unprepare() 88 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); in mtk_hdmi_pll_unprepare() 89 mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); in mtk_hdmi_pll_unprepare() 126 mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PRED_IMP); in mtk_hdmi_pll_set_rate() 182 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); in mtk_hdmi_phy_enable_tmds() 208 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN); in mtk_hdmi_phy_disable_tmds() 210 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); in mtk_hdmi_phy_disable_tmds() 212 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); in mtk_hdmi_phy_disable_tmds() [all …]
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H A D | phy-mtk-hdmi-mt8195.c | 39 mtk_phy_clear_bits(regs + HDMI20_CLK_CFG, REG_TXC_DIV); in mtk_phy_tmds_clk_ratio() 47 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_XTAL_SEL); in mtk_hdmi_pll_sel_src() 48 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_RESPLL_SEL); in mtk_hdmi_pll_sel_src() 51 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITXPLL_REF_CK_SEL); in mtk_hdmi_pll_sel_src() 67 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_HIKVCO); in mtk_hdmi_pll_perf() 97 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_VREF_SEL); in mtk_hdmi_pll_set_hw() 109 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_EN); in mtk_hdmi_pll_set_hw() 197 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_PIXEL_CLOCK_SEL); in mtk_hdmi_pll_set_hw() 377 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD); in mtk_hdmi_pll_prepare() 397 mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_BIAS_EN); in mtk_hdmi_pll_unprepare() [all …]
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H A D | phy-mtk-ufs.c | 66 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON); in ufs_mtk_phy_set_active() 69 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN); in ufs_mtk_phy_set_active() 70 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN); in ufs_mtk_phy_set_active() 74 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON); in ufs_mtk_phy_set_active() 77 mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_ISO_EN); in ufs_mtk_phy_set_active() 78 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN); in ufs_mtk_phy_set_active() 82 mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); in ufs_mtk_phy_set_active() 88 mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); in ufs_mtk_phy_set_active() 100 mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_AC, RX_SQ_EN); in ufs_mtk_phy_set_deep_hibern() 108 mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_PWR_ON); in ufs_mtk_phy_set_deep_hibern() [all …]
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H A D | phy-mtk-mipi-dsi-mt8183.c | 75 mtk_phy_clear_bits(base + MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS); in mtk_mipi_tx_pll_enable() 78 mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN); in mtk_mipi_tx_pll_enable() 80 mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); in mtk_mipi_tx_pll_enable() 94 mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN); in mtk_mipi_tx_pll_disable() 97 mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); in mtk_mipi_tx_pll_disable() 143 mtk_phy_clear_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_on_signal() 144 mtk_phy_clear_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_on_signal() 145 mtk_phy_clear_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_on_signal() 146 mtk_phy_clear_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_on_signal() 147 mtk_phy_clear_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_on_signal()
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H A D | phy-mtk-mipi-dsi-mt8173.c | 180 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); in mtk_mipi_tx_pll_prepare() 205 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_SSC_EN); in mtk_mipi_tx_pll_prepare() 221 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); in mtk_mipi_tx_pll_unprepare() 223 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_TOP, RG_DSI_MPPLL_PRESERVE); in mtk_mipi_tx_pll_unprepare() 229 mtk_phy_clear_bits(base + MIPITX_DSI_TOP_CON, RG_DSI_LNT_HS_BIAS_EN); in mtk_mipi_tx_pll_unprepare() 231 mtk_phy_clear_bits(base + MIPITX_DSI_CON, in mtk_mipi_tx_pll_unprepare() 234 mtk_phy_clear_bits(base + MIPITX_DSI_BG_CON, in mtk_mipi_tx_pll_unprepare() 237 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_DIV_MSK); in mtk_mipi_tx_pll_unprepare() 263 mtk_phy_clear_bits(mipi_tx->regs + MIPITX_DSI_TOP_CON, in mtk_mipi_tx_power_on_signal() 277 mtk_phy_clear_bits(mipi_tx->regs + reg, RG_DSI_LNTx_LDOOUT_EN); in mtk_mipi_tx_power_off_signal()
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H A D | phy-mtk-hdmi-mt8173.c | 94 mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_MHLCK_EN); in mtk_hdmi_pll_prepare() 110 mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); in mtk_hdmi_pll_unprepare() 111 mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); in mtk_hdmi_pll_unprepare() 113 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN); in mtk_hdmi_pll_unprepare() 115 mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); in mtk_hdmi_pll_unprepare() 116 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV); in mtk_hdmi_pll_unprepare() 117 mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); in mtk_hdmi_pll_unprepare() 179 mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_PRD_IMP_EN); in mtk_hdmi_pll_set_rate() 240 mtk_phy_clear_bits(hdmi_phy->regs + HDMI_CON3, in mtk_hdmi_phy_disable_tmds()
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H A D | phy-mtk-tphy.c | 738 mtk_phy_clear_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); in hs_slew_rate_calibrate() 741 mtk_phy_clear_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); in hs_slew_rate_calibrate() 761 mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN); in hs_slew_rate_calibrate() 825 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, in u2_phy_instance_init() 828 mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_UART_EN); in u2_phy_instance_init() 835 mtk_phy_clear_bits(com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK); in u2_phy_instance_init() 851 mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN); in u2_phy_instance_init() 873 mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_SESSEND); in u2_phy_instance_power_on() 916 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_SUSPENDM); in u2_phy_instance_exit() 1000 mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD, in pcie_phy_instance_power_on() [all …]
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H A D | phy-mtk-xsphy.c | 142 mtk_phy_clear_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); in u2_phy_slew_rate_calibrate() 145 mtk_phy_clear_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); in u2_phy_slew_rate_calibrate() 164 mtk_phy_clear_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN); in u2_phy_slew_rate_calibrate() 173 mtk_phy_clear_bits(pbase + XSP_USBPHYACR6, P2A6_RG_BC11_SW_EN); in u2_phy_instance_init() 199 mtk_phy_clear_bits(pbase + XSP_USBPHYACR6, P2A6_RG_OTG_VBUSCMP_EN); in u2_phy_instance_power_off()
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H A D | phy-mtk-io.h | 14 static inline void mtk_phy_clear_bits(void __iomem *reg, u32 bits) in mtk_phy_clear_bits() function
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