39 		mtk_phy_clear_bits(regs + HDMI20_CLK_CFG, REG_TXC_DIV);  in mtk_phy_tmds_clk_ratio()
47 	mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_XTAL_SEL);  in mtk_hdmi_pll_sel_src()
48 	mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_RESPLL_SEL);  in mtk_hdmi_pll_sel_src()
51 	mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITXPLL_REF_CK_SEL);  in mtk_hdmi_pll_sel_src()
65 	mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_IBAND_FIX_EN);  in mtk_hdmi_pll_perf()
66 	mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14);  in mtk_hdmi_pll_perf()
67 	mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_HIKVCO);  in mtk_hdmi_pll_perf()
97 	mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_VREF_SEL);  in mtk_hdmi_pll_set_hw()
99 	mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_VREF_SELB);  in mtk_hdmi_pll_set_hw()
109 	mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_EN);  in mtk_hdmi_pll_set_hw()
157 	mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14);  in mtk_hdmi_pll_set_hw()
197 	mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_PIXEL_CLOCK_SEL);  in mtk_hdmi_pll_set_hw()
200 		mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_PIXEL_CLOCK);  in mtk_hdmi_pll_set_hw()
370 	mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D0_EN);  in mtk_hdmi_pll_prepare()
371 	mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D1_EN);  in mtk_hdmi_pll_prepare()
372 	mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_D2_EN);  in mtk_hdmi_pll_prepare()
373 	mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_FRL_CK_EN);  in mtk_hdmi_pll_prepare()
377 	mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD);  in mtk_hdmi_pll_prepare()
384 	mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_ISO_EN);  in mtk_hdmi_pll_prepare()
386 	mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD);  in mtk_hdmi_pll_prepare()
397 	mtk_phy_clear_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_BIAS_EN);  in mtk_hdmi_pll_unprepare()
398 	mtk_phy_clear_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_CKLDO_EN);  in mtk_hdmi_pll_unprepare()
399 	mtk_phy_clear_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDO_EN);  in mtk_hdmi_pll_unprepare()
405 	mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_PWR_ON);  in mtk_hdmi_pll_unprepare()
451 		mtk_phy_clear_bits(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_EN);  in vtx_signal_en()