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/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Drenesas,riic.yaml32 - description: Transmit End Interrupt
33 - description: Receive Data Full Interrupt
34 - description: Transmit Data Empty Interrupt
35 - description: Stop Condition Detection Interrupt
36 - description: Start Condition Detection Interrupt
37 - description: NACK Reception Interrupt
38 - description: Arbitration-Lost Interrupt
39 - description: Timeout Interrupt
/openbmc/linux/drivers/irqchip/
H A DKconfig306 bool "Xilinx Interrupt Controller IP"
417 tristate "Meson GPIO Interrupt Multiplexer"
460 bool "C-SKY APB Interrupt Controller"
498 bool "Loongson-1 Interrupt Controller"
573 bool "Loongson Local I/O Interrupt Controller"
582 bool "Loongson Extend I/O Interrupt Controller"
637 bool "MStar Interrupt Controller"
643 Support MStar Interrupt Controller.
646 bool "Nuvoton WPCM450 Advanced Interrupt Controller"
657 bool "Apple Interrupt Controller (AIC)"
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Drenesas,intc-irqpin.yaml7 title: Renesas Interrupt Controller (INTC) for external pins
25 - description: Interrupt control register
26 - description: Interrupt priority register
27 - description: Interrupt source register
28 - description: Interrupt mask register
29 - description: Interrupt mask clear register
30 - description: Interrupt control register for ICR0 with IRLM0 bit
H A Dcsky,mpintc.txt2 C-SKY Multi-processors Interrupt Controller
5 C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860
8 Interrupt number definition:
13 Interrupt trigger mode: (Defined in dt-bindings/interrupt-controller/irq.h)
H A Dti,sci-intr.yaml7 title: Texas Instruments K3 Interrupt Router
16 The Interrupt Router (INTR) module provides a mechanism to mux M
18 to be driven per N output. An Interrupt Router can either handle edge
21 Interrupt Router
74 Interrupt ranges that converts the INTR output hw irq numbers
H A Dimg,pdc-intc.txt1 * ImgTec Powerdown Controller (PDC) Interrupt Controller Binding
30 * Interrupt Specifier Definition
32 Interrupt specifiers consists of 2 cells encoded as follows:
88 // Interrupt source Peripheral 0
102 // Interrupt source SysWake 0 that is active-low level-sensitive
H A Dkontron,sl28cpld-intc.yaml7 title: Interrupt controller driver for the sl28cpld board management controller
22 0 RTC_INT# Interrupt line from on-board RTC
28 6 watchdog Interrupt of the internal watchdog
H A Dcdns,xtensa-mx.txt1 * Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX)
H A Dti,sci-inta.yaml7 title: Texas Instruments K3 Interrupt Aggregator
16 The Interrupt Aggregator (INTA) provides a centralized machine
21 Interrupt Aggregator
70 Interrupt ranges that converts the INTA output hw irq numbers
H A Dfsl,ls-extirq.yaml7 title: Freescale Layerscape External Interrupt Controller
46 Specifies the Interrupt Polarity Control Register (INTPCR) in the
47 SCFG or the External Interrupt Control Register (IRQCR) in the ISC.
/openbmc/linux/Documentation/arch/loongarch/
H A Dirq-chip-model.rst9 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
59 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
157 - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
/openbmc/qemu/rust/hw/char/pl011/src/
H A Ddevice.rs20 registers::{self, Interrupt},
381 il &= !Interrupt::MS; in loopback_mdmctrl()
531 Interrupt::E
532 | Interrupt::MS
533 | Interrupt::RT as u32
534 | Interrupt::TX as u32
536 Interrupt::RX as u32,
537 Interrupt::TX as u32,
538 Interrupt::RT as u32,
539 Interrupt::MS,
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dlpc32xx-udc.txt8 * USB Device Low Priority Interrupt
9 * USB Device High Priority Interrupt
10 * USB Device DMA Interrupt
11 * External USB Transceiver Interrupt (OTG ATX)
/openbmc/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dirq-chip-model.rst13 中的中断控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（
14 Legacy I/O Interrupt Controller）、EIOINTC（Extended I/O Interrupt Controller）、
15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
26 在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
62 在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
/openbmc/qemu/docs/specs/
H A Dppc-xive.rst6 architecture, called XIVE as "eXternal Interrupt Virtualization
22 - Interrupt Virtualization Source Engine (IVSE), or Source Controller
28 - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
32 - Interrupt Virtualization Presentation Engine (IVPE) or Presentation
39 XIVE Interrupt Controller
137 - Interrupt Priority Register (PIPR)
138 - Interrupt Pending Buffer (IPB)
145 The Thread Interrupt Management registers are accessible through a
146 specific MMIO region, called the Thread Interrupt Management Area
155 Interrupt flow from an O/S perspective
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dallwinner,sun5i-a13-hstimer.yaml28 - description: Timer 0 Interrupt
29 - description: Timer 1 Interrupt
30 - description: Timer 2 Interrupt
31 - description: Timer 3 Interrupt
H A Dsamsung,exynos4210-mct.yaml67 0: Global Timer Interrupt 0
68 1: Global Timer Interrupt 1
69 2: Global Timer Interrupt 2
70 3: Global Timer Interrupt 3
71 4: Local Timer Interrupt 0
72 5: Local Timer Interrupt 1
75 i: Local Timer Interrupt n
H A Dsnps,arc-timer.txt1 Synopsys ARC Local Timer with Interrupt Capabilities
11 - interrupts : single Interrupt going into parent intc
/openbmc/linux/Documentation/scsi/
H A Dhptiop.rst28 0x24 Inbound Interrupt Status Register
29 0x28 Inbound Interrupt Mask Register
30 0x30 Outbound Interrupt Status Register
31 0x34 Outbound Interrupt Mask Register
46 0x24 Inbound Interrupt Status Register
47 0x28 Inbound Interrupt Mask Register
49 0x34 Outbound Interrupt Mask Register
60 0x20404 Inbound Interrupt Mask Register
62 0x2040C Outbound Interrupt Mask Register
97 0x4088 Outbound List Interrupt Cause
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Ddavinci_emac.txt15 4 sources: <Receive Threshold Interrupt
16 Receive Interrupt
17 Transmit Interrupt
18 Miscellaneous Interrupt>
/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dhisilicon,hip07-sec.txt13 - interrupts: Interrupt specifiers.
16 Interrupt 0 is for the SEC unit error queue.
17 Interrupt 2N + 1 is the completion interrupt for queue N.
18 Interrupt 2N + 2 is the error interrupt for queue N.
/openbmc/u-boot/arch/x86/include/asm/arch-baytrail/acpi/
H A Dgpio.asl19 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
48 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
77 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dsocionext,synquacer-spi.yaml37 - description: Receive Interrupt
38 - description: Transmit Interrupt
39 - description: Fault Interrupt
/openbmc/linux/Documentation/virt/kvm/devices/
H A Dxive.rst4 POWER9 eXternal Interrupt Virtualization Engine (XIVE Gen1)
8 - KVM_DEV_TYPE_XIVE POWER9 XIVE Interrupt Controller generation 1
25 1. Thread Interrupt Management Area (TIMA)
27 Each thread has an associated Thread Interrupt Management context
32 - Interrupt Pending Buffer (IPB)
103 Interrupt source number (64-bit)
116 -E2BIG Interrupt source number is out of range
126 Interrupt source number (64-bit)
136 - eisn: Effective Interrupt Source Number
199 Interrupt source number (64-bit)
/openbmc/u-boot/arch/x86/include/asm/arch-tangier/acpi/
H A Dsouthcluster.asl382 Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 30 }
383 Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 23 }
384 Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 52 }
385 Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 51 }
386 Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 50 }
387 Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 27 }
388 Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 49 }

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