124a28e42SRoland Stigge* NXP LPC32xx SoC USB Device Controller (UDC) 224a28e42SRoland Stigge 324a28e42SRoland StiggeRequired properties: 424a28e42SRoland Stigge- compatible: Must be "nxp,lpc3220-udc" 524a28e42SRoland Stigge- reg: Physical base address of the controller and length of memory mapped 624a28e42SRoland Stigge region. 724a28e42SRoland Stigge- interrupts: The USB interrupts: 824a28e42SRoland Stigge * USB Device Low Priority Interrupt 924a28e42SRoland Stigge * USB Device High Priority Interrupt 1024a28e42SRoland Stigge * USB Device DMA Interrupt 1124a28e42SRoland Stigge * External USB Transceiver Interrupt (OTG ATX) 1224a28e42SRoland Stigge- transceiver: phandle of the associated ISP1301 device - this is necessary for 1324a28e42SRoland Stigge the UDC controller for connecting to the USB physical layer 1424a28e42SRoland Stigge 1524a28e42SRoland StiggeExample: 1624a28e42SRoland Stigge 1724a28e42SRoland Stigge isp1301: usb-transceiver@2c { 1824a28e42SRoland Stigge compatible = "nxp,isp1301"; 1924a28e42SRoland Stigge reg = <0x2c>; 2024a28e42SRoland Stigge }; 2124a28e42SRoland Stigge 2224a28e42SRoland Stigge usbd@31020000 { 2324a28e42SRoland Stigge compatible = "nxp,lpc3220-udc"; 2424a28e42SRoland Stigge reg = <0x31020000 0x300>; 2524a28e42SRoland Stigge interrupt-parent = <&mic>; 2624a28e42SRoland Stigge interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; 2724a28e42SRoland Stigge transceiver = <&isp1301>; 2824a28e42SRoland Stigge }; 29