Lines Matching refs:Interrupt

6 architecture, called XIVE as "eXternal Interrupt Virtualization
22 - Interrupt Virtualization Source Engine (IVSE), or Source Controller
28 - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
32 - Interrupt Virtualization Presentation Engine (IVPE) or Presentation
39                 XIVE Interrupt Controller
133 Interrupt Management context. This context is a set of registers which
137 - Interrupt Priority Register  (PIPR)
138 - Interrupt Pending Buffer     (IPB)
145 The Thread Interrupt Management registers are accessible through a
146 specific MMIO region, called the Thread Interrupt Management Area
155 Interrupt flow from an O/S perspective
160 in the register IBP (Interrupt Pending Buffer) to indicate that an
162 Interrupt Priority Register (PIPR) is also updated using the IPB. This
171 Thread Interrupt Management Area.
198 when a notification is triggered. It also models the Thread Interrupt