Searched refs:CP0 (Results 1 – 17 of 17) sorted by relevance
86 * [35-38] CP0 I2C1 and I2C088 * [40,41] CP0 UART1 TX/RX165 * CP0 Serdes Configuration:231 * [26] CP0 10G SFP TX Fault232 * [27] CP0 10G SFP Mode233 * [28] CP0 10G SFP LOS234 * [29] CP0 10G SFP TX Disable
148 /* CON6 on CP0 expansion */157 /* CON5 on CP0 expansion */169 /* CON4 on CP0 expansion */174 /* CON9 on CP0 expansion */179 /* CON10 on CP0 expansion */
78 * [35-38] CP0 I2C1 and I2C0154 * CP0 Serdes Configuration:222 * [29] CP0 10G SFP TX Disable
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
104 /* CON6 on CP0 expansion */111 /* CON5 on CP0 expansion */142 /* CON4 on CP0 expansion */156 /* CON9 on CP0 expansion */176 /* CON10 on CP0 expansion */
271 * [35-38] CP0 I2C1 and I2C0441 * [29] CP0 10G SFP TX Disable
73 @ CP0 and CP1 accessible?76 @ enable access to CP0 and CP1204 @ enable access to CP0 and CP1215 @ disable access to CP0 and CP1313 @ CP0 and CP1 accessible?
524 /* CP0 VDD & VCS : IR35221 */525 /* CP0 VDN & VIO : IR35221 */526 /* CP0 VDDR : IR35221 */
12 /* CP0 helpers */
850 #define CP0 (1 << 0) macro
3516 ref_and_mask = CP0; in cik_hdp_flush_cp_ring_emit()
2663 MIPS CP0 registers (see KVM_REG_MIPS_CP0_* above) have the following id bit