1*4c43a41eSKonstantin Porotchkin// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4c43a41eSKonstantin Porotchkin/* 3*4c43a41eSKonstantin Porotchkin * Copyright (C) 2019 Marvell International Ltd. 4*4c43a41eSKonstantin Porotchkin * 5*4c43a41eSKonstantin Porotchkin * Device tree for the CN9132-DB board. 6*4c43a41eSKonstantin Porotchkin */ 7*4c43a41eSKonstantin Porotchkin 8*4c43a41eSKonstantin Porotchkin#include "cn9132-db.dtsi" 9*4c43a41eSKonstantin Porotchkin 10*4c43a41eSKonstantin Porotchkin/ { 11*4c43a41eSKonstantin Porotchkin model = "Marvell Armada CN9132-DB setup B"; 12*4c43a41eSKonstantin Porotchkin}; 13*4c43a41eSKonstantin Porotchkin 14*4c43a41eSKonstantin Porotchkin/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash. 15*4c43a41eSKonstantin Porotchkin * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated 16*4c43a41eSKonstantin Porotchkin * simultaneously. When NAND controller is enabled, SPI1 should be disabled. 17*4c43a41eSKonstantin Porotchkin */ 18*4c43a41eSKonstantin Porotchkin 19*4c43a41eSKonstantin Porotchkin&cp0_nand_controller { 20*4c43a41eSKonstantin Porotchkin status = "okay"; 21*4c43a41eSKonstantin Porotchkin}; 22*4c43a41eSKonstantin Porotchkin 23