/openbmc/linux/arch/mips/include/asm/ |
H A D | sni.h | 40 #define SNI_PORT_BASE CKSEG1ADDR(0xb4000000) 46 #define PCIMT_UCONF CKSEG1ADDR(0xbfff0004) 49 #define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c) 52 #define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034) 56 #define PCIMT_ITPEND CKSEG1ADDR(0xbfff0054) 65 #define PCIMT_IRQSEL CKSEG1ADDR(0xbfff005c) 67 #define PCIMT_ECCREG CKSEG1ADDR(0xbfff006c) 71 #define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0084) 80 #define PCIMT_UCONF CKSEG1ADDR(0xbfff0000) 83 #define PCIMT_IOMMU CKSEG1ADDR(0xbfff0018) [all …]
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H A D | addrspace.h | 74 #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) macro 81 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) macro
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/openbmc/u-boot/board/imgtec/malta/ |
H A D | malta.c | 38 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0); in malta_lcd_puts() 56 const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION); in malta_core_card() 128 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); in _machine_restart() 140 io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE); in board_early_init_f() 144 io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); in board_early_init_f() 174 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), in pci_init_board() 182 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE), in pci_init_board() 185 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE), in pci_init_board()
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H A D | lowlevel_init.S | 31 PTR_LI t0, CKSEG1ADDR(MALTA_REVISION) 65 PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE) 70 PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE) 97 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE) 119 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE) 154 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
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/openbmc/linux/arch/mips/dec/prom/ |
H A D | identify.c | 74 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC); in prom_init_kn01() 82 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC); in prom_init_kn230() 91 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC); in prom_init_kn02() 100 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL); in prom_init_kn02xa() 101 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY); in prom_init_kn02xa() 110 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL); in prom_init_kn03() 111 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY); in prom_init_kn03()
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/openbmc/linux/arch/mips/dec/ |
H A D | ecc-berr.c | 144 (void *)CKSEG1ADDR(address); in dec_ecc_be_backend() 227 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); in dec_kn02_be_init() 229 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR); in dec_kn02_be_init() 230 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN); in dec_kn02_be_init() 245 volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); in dec_kn03_be_init() 246 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); in dec_kn03_be_init() 248 kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR); in dec_kn03_be_init() 249 kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN); in dec_kn03_be_init()
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H A D | kn02xa-berr.c | 29 volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER); in dec_kn02xa_be_ack() 30 volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR); in dec_kn02xa_be_ack() 40 volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER); in dec_kn02xa_be_backend() 41 volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR); in dec_kn02xa_be_backend() 126 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); in dec_kn02xa_be_init()
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H A D | kn02-irq.c | 30 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in unmask_kn02_irq() 39 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in mask_kn02_irq() 62 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in init_kn02_irqs()
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H A D | kn01-berr.c | 49 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_ack() 62 volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + in dec_kn01_be_backend() 150 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_interrupt() 177 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_init()
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H A D | int-handler.S | 30 #define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR) 31 #define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL) 32 #define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL)
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H A D | reset.c | 17 noret_func_t func = (void *)CKSEG1ADDR(0x1fc00000); in back_to_prom()
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/openbmc/linux/arch/mips/boot/compressed/ |
H A D | uart-16550.c | 13 #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset)) 18 #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset)) 23 #define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset))
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/openbmc/u-boot/arch/mips/mach-ath79/ar933x/ |
H A D | lowlevel_init.S | 81 li t0, CKSEG1ADDR(AR71XX_RESET_BASE) 110 li t0, CKSEG1ADDR(AR933X_RTC_BASE) 135 li t0, CKSEG1ADDR(AR933X_SRIF_BASE) 157 li t0, CKSEG1ADDR(AR71XX_PLL_BASE) 233 li t0, CKSEG1ADDR(AR933X_SRIF_BASE) 271 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
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/openbmc/u-boot/board/imgtec/boston/ |
H A D | boston-regs.h | 11 #define BOSTON_PLAT_BASE CKSEG1ADDR(0x17ffd000) 12 #define BOSTON_LCD_BASE CKSEG1ADDR(0x17fff000)
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/openbmc/u-boot/arch/mips/mach-ath79/qca953x/ |
H A D | lowlevel_init.S | 101 li t0, CKSEG1ADDR(AR71XX_RESET_BASE) 114 li t0, CKSEG1ADDR(QCA953X_RTC_BASE) 127 li t0, CKSEG1ADDR(QCA953X_SRIF_BASE) 134 li t0, CKSEG1ADDR(AR71XX_PLL_BASE) 178 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
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/openbmc/u-boot/arch/mips/include/asm/ |
H A D | addrspace.h | 71 #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) macro 78 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) macro 138 #define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
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/openbmc/linux/arch/mips/lib/ |
H A D | uncached.c | 48 usp = CKSEG1ADDR(sp); in run_uncached() 60 ufunc = CKSEG1ADDR(lfunc); in run_uncached()
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/openbmc/linux/arch/mips/cobalt/ |
H A D | setup.c | 84 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); in plat_mem_setup() 118 setup_8250_early_printk_port(CKSEG1ADDR(0x1c800000), 0, 0); in prom_init()
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H A D | reset.c | 20 #define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000))
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/openbmc/linux/drivers/mtd/devices/ |
H A D | ms02-nv.c | 88 ms02nv_diagp = (ms02nv_uint *)(CKSEG1ADDR(addr + MS02NV_DIAG)); in ms02nv_probe_one() 89 ms02nv_magicp = (ms02nv_uint *)(CKSEG1ADDR(addr + MS02NV_MAGIC)); in ms02nv_probe_one() 277 csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); in ms02nv_init() 283 csr = (volatile u32 *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); in ms02nv_init()
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/openbmc/linux/arch/mips/sgi-ip22/ |
H A D | ip22-gio.c | 276 ptr32 = (void *)CKSEG1ADDR(addr); in ip22_gio_id() 286 ptr8 = (void *)CKSEG1ADDR(addr + 3); in ip22_gio_id() 297 ptr16 = (void *)CKSEG1ADDR(addr + 2); in ip22_gio_id() 318 ptr = (void *)CKSEG1ADDR(addr + HQ2_MYSTERY_OFFS); in ip22_is_gr2()
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/openbmc/linux/arch/mips/fw/sni/ |
H A D | sniprom.c | 35 #define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000) 87 return (void *)CKSEG1ADDR(hwconf); in prom_get_hwconf()
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/openbmc/linux/arch/mips/include/asm/mach-cobalt/ |
H A D | mach-gt64120.h | 12 #define GT64120_BASE CKSEG1ADDR(GT_DEF_BASE)
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/openbmc/linux/arch/mips/generic/ |
H A D | board-sead3.c | 19 #define SEAD_CONFIG CKSEG1ADDR(0x1b100110) 22 #define MIPS_REVISION CKSEG1ADDR(0x1fc00010)
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/openbmc/u-boot/arch/mips/lib/ |
H A D | cache_init.S | 146 PTR_LI t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE) 253 PTR_LI a0, CKSEG1ADDR(CONFIG_MIPS_CACHE_INDEX_BASE) 364 li t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE) 399 PTR_LI t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
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