Home
last modified time | relevance | path

Searched refs:TLB (Results 26 – 50 of 163) sorted by relevance

1234567

/openbmc/linux/Documentation/arch/arm64/
H A Dhugetlbpage.rst19 block of memory. Regardless of the supported size of entries in TLB, block
28 contiguous set of entries that can be cached in a single TLB entry.
/openbmc/linux/Documentation/core-api/
H A Dcachetlb.rst2 Cache and TLB Flushing Under Linux
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
61 running, there will be no entries in the TLB for 'mm' for
76 from the TLB. The 'vma' is the backing structure used by
80 executable (and thus could be in the 'instruction TLB' in
86 is, after running, there will be no entries in the TLB for
104 For example, it could use this event to pre-load TLB
[all …]
H A Ddma-attributes.rst83 the time to try to allocate memory to in a way that gives better TLB
87 - You know that the accesses to this memory won't thrash the TLB.
92 - You know that the penalty of TLB misses while accessing the
/openbmc/linux/arch/arc/kernel/
H A Dentry-arcv2.S34 VECTOR EV_TLBMissI ; Intruction TLB miss
35 VECTOR EV_TLBMissD ; Data TLB miss
98 ;################### Non TLB Exception Handling #############################
161 ; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they
H A Dentry-compact.S105 VECTOR EV_TLBMissI ; 0x108, Instruction TLB miss (0x21)
106 VECTOR EV_TLBMissD ; 0x110, Data TLB miss (0x22)
249 ;################### Non TLB Exception Handling #############################
/openbmc/u-boot/doc/
H A DREADME.mips38 * Probe CPU types, I-/D-cache and TLB size etc. automatically
42 * Initialize TLB entries redardless of their use
/openbmc/linux/arch/x86/power/
H A Dhibernate_asm_64.S37 movq %cr3, %rcx; # flush TLB
128 movq %cr3, %rcx; # flush TLB
H A Dhibernate_asm_32.S58 movl %cr3, %eax; # flush TLB
/openbmc/linux/arch/arm/mm/
H A Dtlb-v4.S38 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate TLB entry
/openbmc/qemu/docs/system/openrisc/
H A Dcpu-features.rst8 - MMU TLB with 128 entries, 1 way
/openbmc/qemu/docs/devel/
H A Dmulti-thread-tcg.rst176 handled with a per-vCPU TLB structure which once populated will allow
178 translated code. It is possible to set flags in the TLB address which
184 - Virtual TLB (for translating guest address->real address)
186 When the TLB tables are updated by a vCPU thread other than their own
195 - TLB Flush All/Page
197 - cross vCPU TLB flush may need other vCPU brought to halt
199 - TLB Flag Update
202 - TLB Update (update a CPUTLBEntry, via tlb_set_page_with_attrs)
213 TLB flag updates are all done atomically and are also protected by the
/openbmc/linux/Documentation/features/vm/TLB/
H A Darch-support.txt4 # description: arch supports deferral of TLB flush until multiple pages are unmapped
/openbmc/qemu/target/arm/tcg/
H A Dsme_helper.c321 #define DO_LD(NAME, TYPE, HOST, TLB) \ argument
330 TYPE val = TLB(env, useronly_clean_ptr(addr), ra); \
334 #define DO_ST(NAME, TYPE, HOST, TLB) \ argument
344 TLB(env, useronly_clean_ptr(addr), val, ra); \
352 #define DO_LDQ(HNAME, VNAME, BE, HOST, TLB) \ argument
366 uint64_t val0 = TLB(env, useronly_clean_ptr(addr), ra); \
367 uint64_t val1 = TLB(env, useronly_clean_ptr(addr + 8), ra); \
377 #define DO_STQ(HNAME, VNAME, BE, HOST, TLB) \ argument
392 TLB(env, useronly_clean_ptr(addr), ptr[BE], ra); \
393 TLB(env, useronly_clean_ptr(addr + 8), ptr[!BE], ra); \
/openbmc/linux/arch/sparc/kernel/
H A Ddtlb_miss.S15 stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Load TLB
H A Ditlb_miss.S19 stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load TLB
/openbmc/linux/arch/mips/cavium-octeon/
H A DKconfig37 bool "Lock the TLB handler in L2"
41 Lock the low level TLB fast path into L2.
/openbmc/linux/arch/powerpc/platforms/8xx/
H A DKconfig118 circumstances. This workaround adds some overhead (a TLB miss
183 bool "Pinned TLB for DATA"
190 bool "Pinned TLB for IMMR"
/openbmc/linux/arch/x86/
H A DKconfig.debug70 bool "Set upper limit of TLB entries to flush one-by-one"
75 This option allows the user to tune the amount of TLB entries the
76 kernel flushes one-by-one instead of doing a full TLB flush. In
79 to -1, the code flushes the whole TLB unconditionally. Otherwise,
80 for positive values of it, the kernel will use single TLB entry
/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Drenesas,ipmmu-vmsa.yaml15 connected to the IPMMU through a port called micro-TLB.
69 The number of the micro-TLB that the device is connected to.
/openbmc/u-boot/arch/arc/
H A DKconfig87 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
/openbmc/linux/Documentation/admin-guide/hw-vuln/
H A Dmultihit.rst6 instruction fetch hits multiple entries in the instruction TLB. This can
47 processors include a structure, called TLB, that caches recent translations.
115 If EPT is disabled or not available on the host, KVM is in control of TLB
/openbmc/qemu/docs/system/i386/
H A Dhyperv.rst108 Enables paravirtualized TLB shoot-down mechanism. On x86 architecture, remote
109 TLB flush procedure requires sending IPIs and waiting for other CPUs to perform
110 local TLB flush. In virtualized environment some virtual CPUs may not even be
113 implements TLB shoot-down through hypervisor enabling the optimization.
243 Allow for extended GVA ranges to be passed to Hyper-V TLB flush hypercalls
250 enabled, it allows L0 (KVM) to directly handle TLB flush hypercalls from L2
/openbmc/linux/Documentation/arch/ia64/
H A Dia64.rst44 obvious targets include making sure we don't flush the TLB
/openbmc/linux/Documentation/admin-guide/mm/
H A Dconcepts.rst71 TLB). Usually TLB is pretty scarce resource and applications with
73 TLB misses.
79 `huge`. Usage of huge pages significantly reduces pressure on TLB,
80 improves TLB hit-rate and thus improves overall system performance.
/openbmc/linux/Documentation/translations/zh_CN/arch/openrisc/
H A Dopenrisc_port.rst109 彻底改变TLB失误处理。

1234567