1b2441318SGreg Kroah-Hartman# SPDX-License-Identifier: GPL-2.0 223a271ecSDavid Daneyif CPU_CAVIUM_OCTEON 35b3b1688SDavid Daney 4c9941158SDavid Daneyconfig CAVIUM_CN63XXP1 5f54619f2SMasanari Iida bool "Enable CN63XXP1 errata workarounds" 6c9941158SDavid Daney default "n" 7c9941158SDavid Daney help 8c9941158SDavid Daney The CN63XXP1 chip requires build time workarounds to 9c9941158SDavid Daney function reliably, select this option to enable them. These 10c9941158SDavid Daney workarounds will cause a slight decrease in performance on 11c9941158SDavid Daney non-CN63XXP1 hardware, so it is recommended to select "n" 12c9941158SDavid Daney unless it is known the workarounds are needed. 13c9941158SDavid Daney 148a837cdbSDavid Daneyconfig CAVIUM_OCTEON_CVMSEG_SIZE 158a837cdbSDavid Daney int "Number of L1 cache lines reserved for CVMSEG memory" 168a837cdbSDavid Daney range 0 54 17*78073b8fSJiaxun Yang default 0 if !CAVIUM_OCTEON_SOC 18*78073b8fSJiaxun Yang default 1 if CAVIUM_OCTEON_SOC 198a837cdbSDavid Daney help 208a837cdbSDavid Daney CVMSEG LM is a segment that accesses portions of the dcache as a 218a837cdbSDavid Daney local memory; the larger CVMSEG is, the smaller the cache is. 228a837cdbSDavid Daney This selects the size of CVMSEG LM, which is in cache blocks. The 238a837cdbSDavid Daney legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is 248a837cdbSDavid Daney between zero and 6192 bytes). 258a837cdbSDavid Daney 269ddebc46SDavid Daneyendif # CPU_CAVIUM_OCTEON 279ddebc46SDavid Daney 289ddebc46SDavid Daneyif CAVIUM_OCTEON_SOC 299ddebc46SDavid Daney 305b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2 315b3b1688SDavid Daney bool "Lock often used kernel code in the L2" 325b3b1688SDavid Daney default "y" 335b3b1688SDavid Daney help 345b3b1688SDavid Daney Enable locking parts of the kernel into the L2 cache. 355b3b1688SDavid Daney 365b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_TLB 375b3b1688SDavid Daney bool "Lock the TLB handler in L2" 385b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 395b3b1688SDavid Daney default "y" 405b3b1688SDavid Daney help 415b3b1688SDavid Daney Lock the low level TLB fast path into L2. 425b3b1688SDavid Daney 435b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_EXCEPTION 445b3b1688SDavid Daney bool "Lock the exception handler in L2" 455b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 465b3b1688SDavid Daney default "y" 475b3b1688SDavid Daney help 485b3b1688SDavid Daney Lock the low level exception handler into L2. 495b3b1688SDavid Daney 505b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 515b3b1688SDavid Daney bool "Lock the interrupt handler in L2" 525b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 535b3b1688SDavid Daney default "y" 545b3b1688SDavid Daney help 555b3b1688SDavid Daney Lock the low level interrupt handler into L2. 565b3b1688SDavid Daney 575b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_INTERRUPT 585b3b1688SDavid Daney bool "Lock the 2nd level interrupt handler in L2" 595b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 605b3b1688SDavid Daney default "y" 615b3b1688SDavid Daney help 625b3b1688SDavid Daney Lock the 2nd level interrupt handler in L2. 635b3b1688SDavid Daney 645b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_MEMCPY 655b3b1688SDavid Daney bool "Lock memcpy() in L2" 665b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 675b3b1688SDavid Daney default "y" 685b3b1688SDavid Daney help 695b3b1688SDavid Daney Lock the kernel's implementation of memcpy() into L2. 705b3b1688SDavid Daney 713e3114acSAlexander Sverdlinconfig CAVIUM_RESERVE32 723e3114acSAlexander Sverdlin int "Memory to reserve for user processes shared region (MB)" 733e3114acSAlexander Sverdlin range 0 1536 743e3114acSAlexander Sverdlin default "0" 753e3114acSAlexander Sverdlin help 763e3114acSAlexander Sverdlin Reserve a shared memory region for user processes to use for hardware 773e3114acSAlexander Sverdlin memory buffers. This is required for 32bit applications to be able to 783e3114acSAlexander Sverdlin send and receive packets directly. Applications access this memory by 793e3114acSAlexander Sverdlin memory mapping /dev/mem for the addresses in /proc/octeon_info. For 803e3114acSAlexander Sverdlin optimal performance with HugeTLBs, keep this size an even number of 813e3114acSAlexander Sverdlin megabytes. 823e3114acSAlexander Sverdlin 830e49caf6SVenkat Subbiahconfig OCTEON_ILM 840e49caf6SVenkat Subbiah tristate "Module to measure interrupt latency using Octeon CIU Timer" 850e49caf6SVenkat Subbiah help 860e49caf6SVenkat Subbiah This driver is a module to measure interrupt latency using the 870e49caf6SVenkat Subbiah the CIU Timers on Octeon. 880e49caf6SVenkat Subbiah 890e49caf6SVenkat Subbiah To compile this driver as a module, choose M here. The module 900e49caf6SVenkat Subbiah will be called octeon-ilm 910e49caf6SVenkat Subbiah 929ddebc46SDavid Daneyendif # CAVIUM_OCTEON_SOC 93