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Searched refs:PLL (Results 201 – 225 of 294) sorted by relevance

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/openbmc/linux/Documentation/hwmon/
H A Dasus_wmi_sensors.rst39 * 1.8V PLL Voltage,
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3588.c668 [b0pll] = PLL(pll_rk3588_core, PLL_B0PLL, "b0pll", mux_pll_p,
671 [b1pll] = PLL(pll_rk3588_core, PLL_B1PLL, "b1pll", mux_pll_p,
674 [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p,
677 [v0pll] = PLL(pll_rk3588, PLL_V0PLL, "v0pll", mux_pll_p,
680 [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p,
683 [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p,
686 [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p,
689 [npll] = PLL(pll_rk3588, PLL_NPLL, "npll", mux_pll_p,
692 [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p,
H A Dclk-rv1108.c154 [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0),
156 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8),
158 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16),
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dda8xx-cfgchip.txt29 PLL DIV4.5 divider
/openbmc/u-boot/board/lego/ev3/
H A DREADME13 only and it takes care of low level configuration (PLL and DDR), we don't use
/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Dthine,thc63lvd1024.yaml73 Power supply for the TTL output, TTL CLOCKOUT signal, LVDS input, PLL and
H A Drenesas,dsi.yaml53 - description: DSI D-PHY PLL multiplied clock
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-ccu.yaml60 - description: Peripherals PLL
H A Dti,lmk04832.yaml61 description: Optional to set VCO frequency of the PLL in Hertz.
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dsamsung,exynos4210-csis.yaml63 description: MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V).
/openbmc/qemu/hw/misc/
H A Dtrace-events116 msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register"
189 …r(uint32_t pll_id, uint32_t old_multiplier, uint32_t new_multiplier) "RCC: PLL %u: vco_multiplier …
190 stm32l4x5_rcc_pll_channel_enable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u ena…
191 stm32l4x5_rcc_pll_channel_disable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u di…
192 …id, uint32_t channel_id, uint32_t old_divider, uint32_t new_divider) "RCC: PLL %u, channel %u: div…
193 …channel_id, uint64_t vco_freq, uint64_t old_freq, uint64_t new_freq) "RCC: PLL %d channel %d updat…
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos7885.c157 PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
160 PLL(pll_1417x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A DKconfig74 PLL, Low-Power, and Reset Control Register (15-30)
/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dmediatek,cci.yaml30 when the original clock source (PLL) is under transition and not
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dqca,ar803x.yaml37 If set, keep the PLL enabled even if there is no link. Useful if you
H A Drockchip-dwmac.yaml78 is not sourced from SoC's PLL, but input from PHY.
/openbmc/linux/Documentation/translations/zh_CN/core-api/
H A Dkernel-api.rst340 "mem"（暂停到RAM）状态可能需要更全面地关闭来自高速PLL和振荡器的时钟，从而限制了可能
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstih418-clock.dtsi31 * A9 PLL.
H A Dstih407-clock.dtsi28 * A9 PLL.
H A Dstih410-clock.dtsi31 * A9 PLL.
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8939-pm8916.dtsi97 regulator-always-on; /* Needed for CPU PLL */
H A Dmsm8916-pm8916.dtsi119 regulator-always-on; /* Needed for CPU PLL */
/openbmc/linux/arch/sh/include/mach-kfr2r09/mach/
H A Dpartner-jet-setup.txt31 LIST "The PLL and FLL values are updated here for the optimal"
/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Dtoshiba,tc358746.yaml43 internal PLL rate smallest possible
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Darm,malidp.yaml54 - description: the pixel clock feeding the output PLL of the processor

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