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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-pll3-clk.yaml7 title: Allwinner A10 Video PLL
H A Darmada3700-tbg-clock.txt17 - reg : must be the register address of North Bridge PLL register
H A Dfsl,flexspi-clock.yaml14 derived from the platform PLL.
H A Dallwinner,sun4i-a10-pll5-clk.yaml7 title: Allwinner A10 DRAM PLL
H A Dqca,ath79-pll.txt1 Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
H A Dimx6sl-clock.yaml22 interrupt for oscillator read or PLL lock.
H A Dtesla,fsd-clock.yaml91 - description: Shared0 PLL div4 clock (from CMU_CMU)
115 - description: Shared0 PLL div6 clock (from CMU_CMU)
H A Dmicrochip,pic32.txt3 Microchip clock controller is consists of few oscillators, PLL, multiplexer
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra62x-clocks.dtsi18 /* Compared to dm814x, dra62x has interconnect clocks on isp PLL */
/openbmc/linux/drivers/clk/
H A DKconfig46 bool "PLL Driver for HSDK platform"
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
202 Given a target output frequency, the driver will set the PLL and
310 of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all
311 features of the PLL are currently supported by the driver. By default,
312 configured bypass mode with this PLL.
319 Support for the APM X-Gene SoC reference, PLL, and device clocks.
475 Not all features of the PLL are currently supported
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,spdif.yaml61 - description: PLL clock source for 8kHz series rate, optional.
62 - description: PLL clock source for 11khz series rate, optional.
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra234-xusb.yaml47 - description: USB PLL
49 - description: I/O PLL
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32mp1.txt52 PLL children node for PLL1 to PLL4 : (see ref manual for details)
58 - cfg: The parameters for PLL configuration in this order:
76 (optional, PLL is in integer mode when absent)
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3368.c130 [apllb] = PLL(pll_rk3066, PLL_APLLB, "apllb", mux_pll_p, 0, RK3368_PLL_CON(0),
132 [aplll] = PLL(pll_rk3066, PLL_APLLL, "aplll", mux_pll_p, 0, RK3368_PLL_CON(4),
134 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),
136 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
138 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
140 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3368_PLL_CON(20),
H A Dclk-rk3128.c159 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
161 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
163 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
165 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos3250.c746 PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
748 PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
750 PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
752 PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",
918 PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",
920 PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
H A Dclk-exynos4.c1151 [apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1153 [mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1155 [epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1157 [vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
1162 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1164 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1166 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1168 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
H A Dclk-exynos5260.c395 PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll",
647 PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll",
965 PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll",
1162 PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll",
1165 PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll",
1168 PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll",
1825 PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll",
1828 PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll",
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dcdns,dphy.yaml24 - description: PLL reference clock
H A Dbrcm,ns2-drd-phy.txt10 crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
/openbmc/u-boot/board/freescale/mpc837xemds/
H A DREADME27 SW4[1-8]= 0000_0110 (core PLL setting)
28 SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash)
/openbmc/linux/Documentation/devicetree/bindings/arm/calxeda/
H A Dhb-sregs.yaml12 management, they also contain some gate and PLL clocks.
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dsnps,arcpgu.txt13 - "pxlclk" for the clock feeding the output PLL of the controller.
/openbmc/linux/Documentation/driver-api/
H A Dsm501.rst71 must be sourced from the same PLL, although they can then
74 attach if the PLL selection is different.
/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Dplatform.S192 .word 0x00005B80 @ PLL
210 .word 0x000071C1 @ PLL
229 .word 0x00005B80 @ PLL
251 .word 0x000071C1 @ PLL
686 ldr r2, =0xC48066C0 @ load PLL parameter for 24Mhz CLKIN (330)
688 ldr r2, =0x93002400 @ load PLL parameter for 24Mhz CLKIN (396)
694 ldr r2, =0x930023E0 @ load PLL parameter for 24Mhz CLKIN (384)
696 ldr r2, =0x930023C0 @ load PLL parameter for 24Mhz CLKIN (372)
698 ldr r2, =0x930023A0 @ load PLL parameter for 24Mhz CLKIN (360)
708 ldr r2, =0xC4806680 @ load PLL parameter for 25Mhz CLKIN (331)
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