1a1f8ebe5SAlexey BrodkinARC PGU
2a1f8ebe5SAlexey Brodkin
3a1f8ebe5SAlexey BrodkinThis is a display controller found on several development boards produced
4a1f8ebe5SAlexey Brodkinby Synopsys. The ARC PGU is an RGB streamer that reads the data from a
5a1f8ebe5SAlexey Brodkinframebuffer and sends it to a single digital encoder (usually HDMI).
6a1f8ebe5SAlexey Brodkin
7a1f8ebe5SAlexey BrodkinRequired properties:
8a1f8ebe5SAlexey Brodkin  - compatible: "snps,arcpgu"
9a1f8ebe5SAlexey Brodkin  - reg: Physical base address and length of the controller's registers.
10a1f8ebe5SAlexey Brodkin  - clocks: A list of phandle + clock-specifier pairs, one for each
11a1f8ebe5SAlexey Brodkin    entry in 'clock-names'.
12a1f8ebe5SAlexey Brodkin  - clock-names: A list of clock names. For ARC PGU it should contain:
13a1f8ebe5SAlexey Brodkin      - "pxlclk" for the clock feeding the output PLL of the controller.
14a1f8ebe5SAlexey Brodkin
15a1f8ebe5SAlexey BrodkinRequired sub-nodes:
16a1f8ebe5SAlexey Brodkin  - port: The PGU connection to an encoder chip.
17a1f8ebe5SAlexey Brodkin
18a1f8ebe5SAlexey BrodkinExample:
19a1f8ebe5SAlexey Brodkin
20a1f8ebe5SAlexey Brodkin/ {
21a1f8ebe5SAlexey Brodkin	...
22a1f8ebe5SAlexey Brodkin
23a1f8ebe5SAlexey Brodkin	pgu@XXXXXXXX {
24a1f8ebe5SAlexey Brodkin		compatible = "snps,arcpgu";
25a1f8ebe5SAlexey Brodkin		reg = <0xXXXXXXXX 0x400>;
26a1f8ebe5SAlexey Brodkin		clocks = <&clock_node>;
27a1f8ebe5SAlexey Brodkin		clock-names = "pxlclk";
28a1f8ebe5SAlexey Brodkin
29a1f8ebe5SAlexey Brodkin		port {
30a1f8ebe5SAlexey Brodkin			pgu_output: endpoint {
31a1f8ebe5SAlexey Brodkin				remote-endpoint = <&hdmi_enc_input>;
32a1f8ebe5SAlexey Brodkin			};
33a1f8ebe5SAlexey Brodkin		};
34a1f8ebe5SAlexey Brodkin	};
35a1f8ebe5SAlexey Brodkin};
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