| /openbmc/linux/drivers/cpufreq/ |
| H A D | sa1110-cpufreq.c | 39 u_char twr; /* write recovery time (ns) */ member
56 .twr = 10,
65 .twr = 8,
74 .twr = 9,
82 .twr = 10,
91 .twr = 16, /* Trdl: 2 CLKs */
100 .twr = 8,
109 .twr = 8,
146 u_int mem_khz, sd_khz, trp, twr; in sdram_calculate_timing() local
164 twr = ns_to_cycles(sdram->twr, mem_khz); in sdram_calculate_timing()
[all …]
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| /openbmc/linux/drivers/memory/ |
| H A D | jedec_ddr_data.c | 39 .tWR = 15000,
60 .tWR = 15000,
81 .tWR = 15000,
102 .tWR = 15000,
123 .tWR = 3,
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| H A D | of_memory.c | 40 ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); in of_get_min_tck()
72 ret |= of_property_read_u32(np, "tWR", &tim->tWR); in of_do_get_timings()
183 ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); in of_lpddr3_get_min_tck()
229 ret |= of_property_read_u32(np, "tWR", &tim->tWR); in of_lpddr3_do_get_timings()
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| H A D | jedec_ddr.h | 152 u32 tWR; member
176 u32 tWR; member
236 u32 tWR; member
265 u32 tWR; member
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| /openbmc/linux/arch/powerpc/platforms/85xx/ |
| H A D | twr_p102x.c | 8 * TWR-P102x Board Setup
102 pr_info("TWR-P1025 board from Freescale Semiconductor\n"); in twr_p1025_setup_arch()
108 .name = "TWR-P1025", in define_machine()
109 .compatible = "fsl,TWR-P1025", in define_machine()
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | elpida_ecb240abacn.dtsi | 14 tWR-min-tck = <3>;
30 tWR = <15000>;
52 tWR = <15000>;
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | ls1021a-twr-duart.dts | 3 * Freescale ls1021a TWR board device tree source
9 #include "ls1021a-twr.dtsi"
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| H A D | ls1021a-twr-lpuart.dts | 3 * Freescale ls1021a TWR board device tree source
9 #include "ls1021a-twr.dtsi"
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| H A D | ls1021a-twr.dtsi | 3 * Freescale ls1021a TWR board common device tree source
11 model = "LS1021A TWR Board";
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| /openbmc/u-boot/arch/arm/mach-omap2/omap4/ |
| H A D | emif.c | 28 .tWR = 15,
52 .tWR = 15,
81 .tWR = 3,
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| H A D | sdram_elpida.c | 195 .tWR = 15,
218 .tWR = 15,
241 .tWR = 15,
263 .tWR = 3,
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| /openbmc/u-boot/arch/arm/include/asm/arch-omap3/ |
| H A D | mem.h | 163 #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
165 #define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
189 #define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */
191 #define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
295 #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
297 #define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
324 #define NUMONYX_TDAL_200 6 /* Twr/Tck + Trp/tck */
326 #define NUMONYX_TDPL_200 3 /* 15/5 = 3 -> 3 (Twr) */
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr2.yaml | 98 tWR-min-tck:
153 tWR-min-tck = <3>;
169 tWR = <15000>;
190 tWR = <15000>;
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| H A D | jedec,lpddr3.yaml | 149 tWR-min-tck:
215 tWR-min-tck = <7>;
238 tWR = <7500>;
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| H A D | jedec,lpddr2-timings.yaml | 77 tWR:
129 tWR = <15000>;
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| H A D | jedec,lpddr3-timings.yaml | 104 tWR:
152 tWR = <7500>;
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| /openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr2_v3s.c | 18 u8 twr = max(ns_to_t(15), 3); in mctl_set_timing_params() local
43 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ in mctl_set_timing_params()
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| H A D | ddr3_1333.c | 18 u8 twr = max(ns_to_t(15), 3); in mctl_set_timing_params() local
43 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 18 u8 twr = max(ns_to_t(15), 3); in mctl_set_timing_params() local
43 u8 twtp = tcwl + 4 + twr + 1; in mctl_set_timing_params()
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| /openbmc/u-boot/board/timll/devkit3250/ |
| H A D | devkit3250_spl.c | 33 .twr = 83000000, /* tWR = tRDL = 2 CLK */
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| /openbmc/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | emif.c | 29 .tWR = 15,
58 .tWR = 3,
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| /openbmc/u-boot/board/work-microwave/work_92105/ |
| H A D | work_92105_spl.c | 26 .twr = 66666666,
46 .twr = 66666666,
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| /openbmc/linux/arch/powerpc/boot/dts/fsl/ |
| H A D | p1025twr.dts | 2 * P1025 TWR Device Tree Source (32-bit address map)
38 compatible = "fsl,TWR-P1025";
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| /openbmc/u-boot/include/configs/ |
| H A D | p1_twr.h | 13 #define CONFIG_BOARDNAME "TWR-P1025"
49 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */
224 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
390 "dtbfile=twr-p1025twr.dtb\0" \
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| /openbmc/u-boot/arch/arm/include/asm/arch-s32v234/ |
| H A D | lpddr2.h | 40 #define MMDC_MDCFG1_VALUE 0x00180E63 /* tRCD=n/a,tRPpb=n/a,tRC=n/a ,tRAS=25 (=47ns),tRPA=n/a,tWR…
50 … 0xC2018030 /* Configure MR1: BL 4, burst type interleaved, wrap control no wrap, tWR cycles 8 */
|