nand\-ecc\-mode (full) in projects: openbmc

Searched +full:nand +full:- +full:ecc +full:- +full:mode (Results 1 – 25 of 391) sorted by relevance

/openbmc/u-boot/arch/arm/mach-uniphier/boot-device/
H A D	boot-device-ld11.c	1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2016-2017 Socionext Inc. 12 #include "boot-device.h" 15 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, 16 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"}, 17 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, 18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, 19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, 20 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, 21 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, [all …]
H A D	boot-device-pxs2.c	1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2015-2017 Socionext Inc. 12 #include "boot-device.h" 15 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, 16 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, 17 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, 18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, 19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, 20 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, 21 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, [all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A D	nvidia-tegra20-nand.txt	`1 NVIDIA Tegra NAND Flash controller 4 - compatible: Must be one of: 5 - "nvidia,tegra20-nand" 6 - reg: MMIO address range 7 - interrupts: interrupt output of the NFC controller 8 - clocks: Must contain an entry for each entry in clock-names. 9 See ../clocks/clock-bindings.txt for details. 10 - clock-names: Must include the following entries: 11 - nand 12 - resets: Must contain an entry for each entry in reset-names. [all …]`
H A D	davinci-nand.txt	1 Device tree bindings for Texas instruments Davinci/Keystone NAND controller 4 NAND interface contains. 7 Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf 8 Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf 12 - compatible: "ti,davinci-nand" 13 "ti,keystone-nand" 15 - reg: Contains 2 offset/length values: 16 - offset and length for the access window. 17 - offset and length for accessing the AEMIF 20 - ti,davinci-chipselect: number of chipselect. Indicates on the [all …]
H A D	hisi504-nand.txt	1 Hisilicon Hip04 Soc NAND controller DT binding 5 - compatible: Should be "hisilicon,504-nfc". 6 - reg: The first contains base physical address and size of 7 NAND controller's registers. The second contains base 8 physical address and size of NAND controller's buffer. 9 - interrupts: Interrupt number for nfc. 10 - nand-bus-width: See nand-controller.yaml. 11 - nand-ecc-mode: Support none and hw ecc mode. 12 - #address-cells: Partition address, should be set 1. 13 - #size-cells: Partition size, should be set 1. [all …]
H A D	marvell,nand-controller.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Marvell NAND Flash Controller (NFC) 10 - Miquel Raynal <miquel.raynal@bootlin.com> 15 - items: 16 - const: marvell,armada-8k-nand-controller 17 - const: marvell,armada370-nand-controller 18 - enum: [all …]`
H A D	atmel-nand.txt	1 Atmel NAND flash controller bindings 3 The NAND flash controller node should be defined under the EBI bus (see 4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt). 5 One or several NAND devices can be defined under this NAND controller. 6 The NAND controller might be connected to an ECC engine. 8 * NAND controller bindings: 11 - compatible: should be one of the following 12 "atmel,at91rm9200-nand-controller" 13 "atmel,at91sam9260-nand-controller" 14 "atmel,at91sam9261-nand-controller" [all …]
H A D	rockchip,nand-controller.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip SoCs NAND FLASH Controller (NFC) 10 - $ref: nand-controller.yaml# 13 - Heiko Stuebner <heiko@sntech.de> 18 - const: rockchip,px30-nfc 19 - const: rockchip,rk2928-nfc 20 - const: rockchip,rv1108-nfc [all …]`
H A D	vf610-nfc.txt	1 Freescale's NAND flash controller (NFC) 3 This variant of the Freescale NAND flash controller (NFC) can be found on 7 - compatible: Should be set to "fsl,vf610-nfc". 8 - reg: address range of the NFC. 9 - interrupts: interrupt of the NFC. 10 - #address-cells: shall be set to 1. Encode the nand CS. 11 - #size-cells : shall be set to 0. 12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>; 13 - assigned-clock-rates: The NAND bus timing is derived from this clock 14 rate and should not exceed maximum timing for any NAND memory chip [all …]
H A D	mediatek,mtk-nfc.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mtd/mediatek,mtk-nfc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: MediaTek(MTK) SoCs raw NAND FLASH controller (NFC) 10 - Xiangsheng Hou <xiangsheng.hou@mediatek.com> 15 - mediatek,mt2701-nfc 16 - mediatek,mt2712-nfc 17 - mediatek,mt7622-nfc 21 - description: Base physical address and size of NFI. [all …]`
/openbmc/u-boot/drivers/mtd/nand/raw/
H A D	omap_gpmc.c	1 // SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com> 15 #include <nand.h> 54 * omap_nand_hwcontrol - Set the address pointers corretly for the 62 int cs = info->cs; in omap_nand_hwcontrol() 70 this->IO_ADDR_W = (void __iomem )&gpmc_cfg->cs[cs].nand_cmd; in omap_nand_hwcontrol() 73 this->IO_ADDR_W = (void __iomem )&gpmc_cfg->cs[cs].nand_adr; in omap_nand_hwcontrol() 76 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; in omap_nand_hwcontrol() 81 writeb(cmd, this->IO_ADDR_W); in omap_nand_hwcontrol() 89 return gpmc_cfg->status & (1 << (8 + info->ws)); in omap_dev_ready() [all …]
H A D	sunxi_nand.c	1 // SPDX-License-Identifier: GPL-2.0+ 7 * https://github.com/yuq/sunxi-nfc-mtd 10 * https://github.com/hno/Allwinner-Info 30 #include <nand.h> 78 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8) 114 #define NFC_ADR_NUM(x) (((x) - 1) << 16) 171 * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy 172 * pin of the NAND flash chip must be connected to one of the 173 * native NAND R/B pins (those which can be muxed to the NAND 176 * pin of the NAND flash chip must be connected to a GPIO capable [all …]
H A D	lpc32xx_nand_mlc.c	1 // SPDX-License-Identifier: GPL-2.0+ 3 * LPC32xx MLC NAND flash controller driver 10 * The MLC NAND flash controller provides hardware Reed-Solomon ECC 11 * covering in- and out-of-band data together. Therefore, in- and out- 12 * of-band data must be written together in order to have a valid ECC. 14 * Consequently, pages with meaningful in-band data are written with 15 * blank (all-ones) out-of-band data and a valid ECC, and any later 16 * out-of-band data write will void the ECC. 18 * Therefore, code which reads such late-written out-of-band data 19 * should not rely on the ECC validity. [all …]
H A D	fsmc_nand.c	1 // SPDX-License-Identifier: GPL-2.0+ 11 #include <nand.h> 24 * ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of 61 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 138 bytes 62 of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118 97 * ECC placement definitions in oobfree type format 98 * There are 13 bytes of ecc for every 512 byte block and it has to be read 101 * Managing the ecc bytes in the following way makes it easier for software to 102 * read ecc bytes consecutive to data bytes. This way is similar to 103 * oobfree structure maintained already in u-boot nand driver [all …]
H A D	Kconfig	`2 menuconfig NAND config 3 bool "Raw NAND Device Support" 4 if NAND 9 This option, if enabled, provides more flexible and linux-like 10 NAND initialization process. 15 Omit standard ECC layouts to safe space. Select this if your driver 16 is known to provide its own ECC layout. 19 bool "Support Atmel NAND controller" 22 Enable this driver for NAND flash platforms using an Atmel NAND 28 bool "Atmel Hardware ECC" [all …]`
H A D	atmel_nand.c	`1 // SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2007-2008 9 * Add Programmable Multibit ECC support for various AT91 SoC 18 #include <nand.h> 30 #include "atmel_nand_ecc.h" /* Hardware ECC registers / 71 Return number of ecc bytes per sector according to sector size and 77 * 2-bits 4-bytes 4-bytes 78 * 4-bits 7-bytes 7-bytes 79 * 8-bits 13-bytes 14-bytes 80 * 12-bits 20-bytes 21-bytes [all …]`
H A D	davinci_nand.c	`1 // SPDX-License-Identifier: GPL-2.0+ 3 * NAND driver for TI DaVinci based boards. 7 * Based on Linux DaVinci NAND driver by TI. Original copyright follows: 12 * linux/drivers/mtd/nand/raw/nand_davinci.c 14 * NAND Flash Driver 18 * ---------------------------------------------------------------------------- 20 * ---------------------------------------------------------------------------- 23 * This is a device driver for the NAND flash device found on the 28 - 33 #include <nand.h> [all …]`
/openbmc/linux/drivers/mtd/nand/raw/
H A D	fsmc_nand.c	`1 // SPDX-License-Identifier: GPL-2.0 5 * Driver for NAND portions 11 * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8) 20 #include <linux/dma-direction.h> 21 #include <linux/dma-mapping.h> 29 #include <linux/mtd/nand-ecc-sw-hamming.h> 37 #include <mtd/mtd-abi.h> 61 /* fsmc controller registers for NAND flash / 99 TOUDEL = 7ns (Output delay from the flip-flops to the board) 120 * struct fsmc_nand_data - structure for FSMC NAND device state [all …]`
H A D	nand_base.c	1 // SPDX-License-Identifier: GPL-2.0-only 4 * This is the generic MTD driver for NAND flash devices. It should be 5 * capable of working with almost all NAND chips currently available. 8 * http://www.linux-mtd.infradead.org/doc/nand.html 11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de) 21 * Check, if mtd->ecctype should be set to MTD_ECC_HW 22 * if we have HW ECC support. 37 #include <linux/mtd/nand.h> 38 #include <linux/mtd/nand-ecc-sw-hamming.h> 39 #include <linux/mtd/nand-ecc-sw-bch.h> [all …]
H A D	omap2.c	`1 // SPDX-License-Identifier: GPL-2.0-only 10 #include <linux/dma-mapping.h> 18 #include <linux/mtd/nand-ecc-sw-bch.h> 21 #include <linux/omap-dma.h> 29 #include <linux/omap-gpmc.h> 30 #include <linux/platform_data/mtd-nand-omap2.h> 32 #define DRIVER_NAME "omap2-nand" 122 /* GPMC ecc engine settings for read / 123 #define BCH_WRAPMODE_1 1 / BCH wrap mode 1 / 129 / GPMC ecc engine settings for write */ [all …]`
H A D	sunxi_nand.c	1 // SPDX-License-Identifier: GPL-2.0+ 6 * https://github.com/yuq/sunxi-nfc-mtd 9 * https://github.com/hno/Allwinner-Info 16 #include <linux/dma-mapping.h> 70 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8) 107 #define NFC_ADR_NUM(x) (((x) - 1) << 16) 161 * struct sunxi_nand_chip_sel - store 194 struct nand_chip nand; global() member 195 struct sunxi_nand_hw_ecc ecc; global() member 203 to_sunxi_nand(struct nand_chip * nand) to_sunxi_nand() argument 415 sunxi_nfc_select_chip(struct nand_chip * nand,unsigned int cs) sunxi_nfc_select_chip() argument 446 sunxi_nfc_read_buf(struct nand_chip * nand,uint8_t * buf,int len) sunxi_nfc_read_buf() argument 483 sunxi_nfc_write_buf(struct nand_chip * nand,const uint8_t * buf,int len) sunxi_nfc_write_buf() argument 602 sunxi_nfc_randomizer_state(struct nand_chip * nand,int page,bool ecc) sunxi_nfc_randomizer_state() argument 603 sunxi_nfc_randomizer_state(struct nand_chip * nand,int page,bool ecc) sunxi_nfc_randomizer_state() argument 622 sunxi_nfc_randomizer_config(struct nand_chip * nand,int page,bool ecc) sunxi_nfc_randomizer_config() argument 623 sunxi_nfc_randomizer_config(struct nand_chip * nand,int page,bool ecc) sunxi_nfc_randomizer_config() argument 638 sunxi_nfc_randomizer_enable(struct nand_chip * nand) sunxi_nfc_randomizer_enable() argument 649 sunxi_nfc_randomizer_disable(struct nand_chip * nand) sunxi_nfc_randomizer_disable() argument 660 sunxi_nfc_randomize_bbm(struct nand_chip * nand,int page,u8 * bbm) sunxi_nfc_randomize_bbm() argument 668 sunxi_nfc_randomizer_write_buf(struct nand_chip * nand,const uint8_t * buf,int len,bool ecc,int page) sunxi_nfc_randomizer_write_buf() argument 670 sunxi_nfc_randomizer_write_buf(struct nand_chip * nand,const uint8_t * buf,int len,bool ecc,int page) sunxi_nfc_randomizer_write_buf() argument 678 sunxi_nfc_randomizer_read_buf(struct nand_chip * nand,uint8_t * buf,int len,bool ecc,int page) sunxi_nfc_randomizer_read_buf() argument 679 sunxi_nfc_randomizer_read_buf(struct nand_chip * nand,uint8_t * buf,int len,bool ecc,int page) sunxi_nfc_randomizer_read_buf() argument 687 sunxi_nfc_hw_ecc_enable(struct nand_chip * nand) sunxi_nfc_hw_ecc_enable() argument 695 sunxi_nfc_hw_ecc_disable(struct nand_chip * nand) sunxi_nfc_hw_ecc_disable() argument 715 sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct nand_chip * nand,u8 * oob,int step,bool bbm,int page) sunxi_nfc_hw_ecc_get_prot_oob_bytes() argument 728 sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct nand_chip * nand,const u8 * oob,int step,bool bbm,int page) sunxi_nfc_hw_ecc_set_prot_oob_bytes() argument 746 sunxi_nfc_hw_ecc_update_stats(struct nand_chip * nand,unsigned int * max_bitflips,int ret) sunxi_nfc_hw_ecc_update_stats() argument 759 sunxi_nfc_hw_ecc_correct(struct nand_chip * nand,u8 * data,u8 * oob,int step,u32 status,bool * erased) sunxi_nfc_hw_ecc_correct() argument 763 struct nand_ecc_ctrl ecc = &nand->ecc; sunxi_nfc_hw_ecc_correct() local 795 sunxi_nfc_hw_ecc_read_chunk(struct nand_chip nand,u8 * data,int data_off,u8 * oob,int oob_off,int * cur_off,unsigned int * max_bitflips,bool bbm,bool oob_required,int page) sunxi_nfc_hw_ecc_read_chunk() argument 803 struct nand_ecc_ctrl ecc = &nand->ecc; sunxi_nfc_hw_ecc_read_chunk() local 876 sunxi_nfc_hw_ecc_read_extra_oob(struct nand_chip nand,u8 * oob,int * cur_off,bool randomize,int page) sunxi_nfc_hw_ecc_read_extra_oob() argument 881 struct nand_ecc_ctrl ecc = &nand->ecc; sunxi_nfc_hw_ecc_read_extra_oob() local 902 sunxi_nfc_hw_ecc_read_chunks_dma(struct nand_chip nand,uint8_t * buf,int oob_required,int page,int nchunks) sunxi_nfc_hw_ecc_read_chunks_dma() argument 909 struct nand_ecc_ctrl ecc = &nand->ecc; sunxi_nfc_hw_ecc_read_chunks_dma() local 1030 sunxi_nfc_hw_ecc_write_chunk(struct nand_chip nand,const u8 * data,int data_off,const u8 * oob,int oob_off,int * cur_off,bool bbm,int page) sunxi_nfc_hw_ecc_write_chunk() argument 1037 struct nand_ecc_ctrl ecc = &nand->ecc; sunxi_nfc_hw_ecc_write_chunk() local 1069 sunxi_nfc_hw_ecc_write_extra_oob(struct nand_chip nand,u8 * oob,int * cur_off,int page) sunxi_nfc_hw_ecc_write_extra_oob() argument 1074 struct nand_ecc_ctrl ecc = &nand->ecc; sunxi_nfc_hw_ecc_write_extra_oob() local 1091 sunxi_nfc_hw_ecc_read_page(struct nand_chip nand,uint8_t * buf,int oob_required,int page) sunxi_nfc_hw_ecc_read_page() argument 1095 struct nand_ecc_ctrl ecc = &nand->ecc; sunxi_nfc_hw_ecc_read_page() local 1131 sunxi_nfc_hw_ecc_read_page_dma(struct nand_chip nand,u8 * buf,int oob_required,int page) sunxi_nfc_hw_ecc_read_page_dma() argument 1149 sunxi_nfc_hw_ecc_read_subpage(struct nand_chip * nand,u32 data_offs,u32 readlen,u8 * bufpoi,int page) sunxi_nfc_hw_ecc_read_subpage() argument 1154 struct nand_ecc_ctrl ecc = &nand->ecc; sunxi_nfc_hw_ecc_read_subpage() local 1185 sunxi_nfc_hw_ecc_read_subpage_dma(struct nand_chip nand,u32 data_offs,u32 readlen,u8 * buf,int page) sunxi_nfc_hw_ecc_read_subpage_dma() argument 1205 sunxi_nfc_hw_ecc_write_page(struct nand_chip * nand,const uint8_t * buf,int oob_required,int page) sunxi_nfc_hw_ecc_write_page() argument 1210 struct nand_ecc_ctrl ecc = &nand->ecc; sunxi_nfc_hw_ecc_write_page() local 1241 sunxi_nfc_hw_ecc_write_subpage(struct nand_chip nand,u32 data_offs,u32 data_len,const u8 * buf,int oob_required,int page) sunxi_nfc_hw_ecc_write_subpage() argument 1247 struct nand_ecc_ctrl ecc = &nand->ecc; sunxi_nfc_hw_ecc_write_subpage() local 1275 sunxi_nfc_hw_ecc_write_page_dma(struct nand_chip nand,const u8 * buf,int oob_required,int page) sunxi_nfc_hw_ecc_write_page_dma() argument 1281 struct nand_ecc_ctrl ecc = &nand->ecc; sunxi_nfc_hw_ecc_write_page_dma() local 1346 sunxi_nfc_hw_ecc_read_oob(struct nand_chip nand,int page) sunxi_nfc_hw_ecc_read_oob() argument 1353 sunxi_nfc_hw_ecc_write_oob(struct nand_chip * nand,int page) sunxi_nfc_hw_ecc_write_oob() argument 1389 sunxi_nfc_setup_interface(struct nand_chip * nand,int csline,const struct nand_interface_config * conf) sunxi_nfc_setup_interface() argument 1562 struct nand_chip nand = mtd_to_nand(mtd); sunxi_nand_ooblayout_ecc() local 1563 struct nand_ecc_ctrl ecc = &nand->ecc; sunxi_nand_ooblayout_ecc() local 1577 struct nand_chip nand = mtd_to_nand(mtd); sunxi_nand_ooblayout_free() local 1578 struct nand_ecc_ctrl ecc = &nand->ecc; sunxi_nand_ooblayout_free() local 1617 sunxi_nand_hw_ecc_ctrl_init(struct nand_chip * nand,struct nand_ecc_ctrl * ecc,struct device_node * np) sunxi_nand_hw_ecc_ctrl_init() argument 1618 sunxi_nand_hw_ecc_ctrl_init(struct nand_chip * nand,struct nand_ecc_ctrl * ecc,struct device_node * np) sunxi_nand_hw_ecc_ctrl_init() argument 1724 sunxi_nand_attach_chip(struct nand_chip * nand) sunxi_nand_attach_chip() argument 1728 struct nand_ecc_ctrl ecc = &nand->ecc; sunxi_nand_attach_chip() local 1764 sunxi_nfc_exec_subop(struct nand_chip nand,const struct nand_subop * subop) sunxi_nfc_exec_subop() argument 1860 sunxi_nfc_soft_waitrdy(struct nand_chip * nand,const struct nand_subop * subop) sunxi_nfc_soft_waitrdy() argument 1897 sunxi_nfc_exec_op(struct nand_chip * nand,const struct nand_operation * op,bool check_only) sunxi_nfc_exec_op() argument 1943 struct nand_chip *nand; sunxi_nand_chip_init() local [all...]
/openbmc/linux/drivers/mtd/nand/
H A D	ecc-mxic.c	`1 // SPDX-License-Identifier: GPL-2.0 3 * Support for Macronix external hardware ECC engine for NAND devices, also 10 #include <linux/dma-mapping.h> 18 #include <linux/mtd/nand.h> 19 #include <linux/mtd/nand-ecc-mxic.h> 53 /* ECC Chunk Size / 63 / ECC Chunk Count / 98 / ECC machinery / 124 static struct mxic_ecc_engine nand_to_mxic(struct nand_device nand) in nand_to_mxic() argument 126 struct nand_ecc_engine eng = nand->ecc.engine; in nand_to_mxic() [all …]`
/openbmc/u-boot/include/linux/mtd/
H A D	rawnand.h	`1 /* SPDX-License-Identifier: GPL-2.0+ / 3 Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 8 * Contains standard defines and IDs for NAND flash devices 35 /* Scan and identify a NAND device / 39 and override command or ECC setup according to flash type. 45 /* Free resources held by the NAND device / 77 Standard NAND flash commands 104 /* Extended commands for AG-AND device / 115 / multi-bank error status (banks 0-3) */ 123 #define NAND_CMD_NONE -1 [all …]`
/openbmc/linux/drivers/mtd/nand/raw/ingenic/
H A D	ingenic_nand_drv.c	`1 // SPDX-License-Identifier: GPL-2.0 3 * Ingenic JZ47xx NAND driver 23 #include <linux/jz4780-nemc.h> 27 #define DRV_NAME "ingenic-nand" 44 struct ingenic_ecc ecc; member 75 struct nand_ecc_ctrl ecc = &chip->ecc; in qi_lb60_ooblayout_ecc() local 77 if (section \|\| !ecc->total) in qi_lb60_ooblayout_ecc() 78 return -ERANGE; in qi_lb60_ooblayout_ecc() 80 oobregion->length = ecc->total; in qi_lb60_ooblayout_ecc() 81 oobregion->offset = 12; in qi_lb60_ooblayout_ecc() [all …]`
/openbmc/linux/include/linux/mtd/
H A D	nand.h	1 /* SPDX-License-Identifier: GPL-2.0 / 3 Copyright 2017 - Free Electrons 6 * Boris Brezillon <boris.brezillon@free-electrons.com> 18 * struct nand_memory_organization - Memory organization structure 19 * @bits_per_cell: number of bits per NAND cell 27 * @ntargets: total number of targets exposed by the NAND device 55 * struct nand_row_converter - Information needed to convert an absolute offset 67 * struct nand_pos - NAND position object 68 * @target: the NAND target/die 74 * These information are usually used by specific sub-layers to select the [all …]

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