1bb696344SBoris Brezillon // SPDX-License-Identifier: GPL-2.0
293db446aSBoris Brezillon /*
393db446aSBoris Brezillon * ST Microelectronics
493db446aSBoris Brezillon * Flexible Static Memory Controller (FSMC)
593db446aSBoris Brezillon * Driver for NAND portions
693db446aSBoris Brezillon *
793db446aSBoris Brezillon * Copyright © 2010 ST Microelectronics
893db446aSBoris Brezillon * Vipin Kumar <vipin.kumar@st.com>
993db446aSBoris Brezillon * Ashish Priyadarshi
1093db446aSBoris Brezillon *
1193db446aSBoris Brezillon * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
1293db446aSBoris Brezillon * Copyright © 2007 STMicroelectronics Pvt. Ltd.
1393db446aSBoris Brezillon * Copyright © 2009 Alessandro Rubini
1493db446aSBoris Brezillon */
1593db446aSBoris Brezillon
1693db446aSBoris Brezillon #include <linux/clk.h>
1793db446aSBoris Brezillon #include <linux/completion.h>
18a4ca0c43SHerve Codina #include <linux/delay.h>
1993db446aSBoris Brezillon #include <linux/dmaengine.h>
2093db446aSBoris Brezillon #include <linux/dma-direction.h>
2193db446aSBoris Brezillon #include <linux/dma-mapping.h>
2293db446aSBoris Brezillon #include <linux/err.h>
2393db446aSBoris Brezillon #include <linux/init.h>
2493db446aSBoris Brezillon #include <linux/module.h>
2593db446aSBoris Brezillon #include <linux/resource.h>
2693db446aSBoris Brezillon #include <linux/sched.h>
2793db446aSBoris Brezillon #include <linux/types.h>
2893db446aSBoris Brezillon #include <linux/mtd/mtd.h>
29ad9ffdceSMiquel Raynal #include <linux/mtd/nand-ecc-sw-hamming.h>
3093db446aSBoris Brezillon #include <linux/mtd/rawnand.h>
3193db446aSBoris Brezillon #include <linux/platform_device.h>
3293db446aSBoris Brezillon #include <linux/of.h>
3393db446aSBoris Brezillon #include <linux/mtd/partitions.h>
3493db446aSBoris Brezillon #include <linux/io.h>
3593db446aSBoris Brezillon #include <linux/slab.h>
3693db446aSBoris Brezillon #include <linux/amba/bus.h>
3793db446aSBoris Brezillon #include <mtd/mtd-abi.h>
3893db446aSBoris Brezillon
3993db446aSBoris Brezillon /* fsmc controller registers for NOR flash */
4093db446aSBoris Brezillon #define CTRL 0x0
4193db446aSBoris Brezillon /* ctrl register definitions */
42fc43f45eSBoris Brezillon #define BANK_ENABLE BIT(0)
43fc43f45eSBoris Brezillon #define MUXED BIT(1)
4493db446aSBoris Brezillon #define NOR_DEV (2 << 2)
45fc43f45eSBoris Brezillon #define WIDTH_16 BIT(4)
46fc43f45eSBoris Brezillon #define RSTPWRDWN BIT(6)
47fc43f45eSBoris Brezillon #define WPROT BIT(7)
48fc43f45eSBoris Brezillon #define WRT_ENABLE BIT(12)
49fc43f45eSBoris Brezillon #define WAIT_ENB BIT(13)
5093db446aSBoris Brezillon
5193db446aSBoris Brezillon #define CTRL_TIM 0x4
5293db446aSBoris Brezillon /* ctrl_tim register definitions */
5393db446aSBoris Brezillon
5493db446aSBoris Brezillon #define FSMC_NOR_BANK_SZ 0x8
5593db446aSBoris Brezillon #define FSMC_NOR_REG_SIZE 0x40
5693db446aSBoris Brezillon
57fc43f45eSBoris Brezillon #define FSMC_NOR_REG(base, bank, reg) ((base) + \
58fc43f45eSBoris Brezillon (FSMC_NOR_BANK_SZ * (bank)) + \
59fc43f45eSBoris Brezillon (reg))
6093db446aSBoris Brezillon
6193db446aSBoris Brezillon /* fsmc controller registers for NAND flash */
628f3931edSBoris Brezillon #define FSMC_PC 0x00
6393db446aSBoris Brezillon /* pc register definitions */
64fc43f45eSBoris Brezillon #define FSMC_RESET BIT(0)
65fc43f45eSBoris Brezillon #define FSMC_WAITON BIT(1)
66fc43f45eSBoris Brezillon #define FSMC_ENABLE BIT(2)
67fc43f45eSBoris Brezillon #define FSMC_DEVTYPE_NAND BIT(3)
68fc43f45eSBoris Brezillon #define FSMC_DEVWID_16 BIT(4)
69fc43f45eSBoris Brezillon #define FSMC_ECCEN BIT(6)
70fc43f45eSBoris Brezillon #define FSMC_ECCPLEN_256 BIT(7)
7193db446aSBoris Brezillon #define FSMC_TCLR_SHIFT (9)
7293db446aSBoris Brezillon #define FSMC_TCLR_MASK (0xF)
7393db446aSBoris Brezillon #define FSMC_TAR_SHIFT (13)
7493db446aSBoris Brezillon #define FSMC_TAR_MASK (0xF)
7593db446aSBoris Brezillon #define STS 0x04
7693db446aSBoris Brezillon /* sts register definitions */
77fc43f45eSBoris Brezillon #define FSMC_CODE_RDY BIT(15)
7893db446aSBoris Brezillon #define COMM 0x08
7993db446aSBoris Brezillon /* comm register definitions */
8093db446aSBoris Brezillon #define FSMC_TSET_SHIFT 0
8193db446aSBoris Brezillon #define FSMC_TSET_MASK 0xFF
8293db446aSBoris Brezillon #define FSMC_TWAIT_SHIFT 8
8393db446aSBoris Brezillon #define FSMC_TWAIT_MASK 0xFF
8493db446aSBoris Brezillon #define FSMC_THOLD_SHIFT 16
8593db446aSBoris Brezillon #define FSMC_THOLD_MASK 0xFF
8693db446aSBoris Brezillon #define FSMC_THIZ_SHIFT 24
8793db446aSBoris Brezillon #define FSMC_THIZ_MASK 0xFF
8893db446aSBoris Brezillon #define ATTRIB 0x0C
8993db446aSBoris Brezillon #define IOATA 0x10
9093db446aSBoris Brezillon #define ECC1 0x14
9193db446aSBoris Brezillon #define ECC2 0x18
9293db446aSBoris Brezillon #define ECC3 0x1C
9393db446aSBoris Brezillon #define FSMC_NAND_BANK_SZ 0x20
9493db446aSBoris Brezillon
9593db446aSBoris Brezillon #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
9693db446aSBoris Brezillon
979472335eSHerve Codina /*
989472335eSHerve Codina * According to SPEAr300 Reference Manual (RM0082)
999472335eSHerve Codina * TOUDEL = 7ns (Output delay from the flip-flops to the board)
1009472335eSHerve Codina * TINDEL = 5ns (Input delay from the board to the flipflop)
1019472335eSHerve Codina */
1029472335eSHerve Codina #define TOUTDEL 7000
1039472335eSHerve Codina #define TINDEL 5000
1049472335eSHerve Codina
10593db446aSBoris Brezillon struct fsmc_nand_timings {
106fc43f45eSBoris Brezillon u8 tclr;
107fc43f45eSBoris Brezillon u8 tar;
108fc43f45eSBoris Brezillon u8 thiz;
109fc43f45eSBoris Brezillon u8 thold;
110fc43f45eSBoris Brezillon u8 twait;
111fc43f45eSBoris Brezillon u8 tset;
11293db446aSBoris Brezillon };
11393db446aSBoris Brezillon
11493db446aSBoris Brezillon enum access_mode {
11593db446aSBoris Brezillon USE_DMA_ACCESS = 1,
11693db446aSBoris Brezillon USE_WORD_ACCESS,
11793db446aSBoris Brezillon };
11893db446aSBoris Brezillon
11993db446aSBoris Brezillon /**
12093db446aSBoris Brezillon * struct fsmc_nand_data - structure for FSMC NAND device state
12193db446aSBoris Brezillon *
122ad71148cSBoris Brezillon * @base: Inherit from the nand_controller struct
12393db446aSBoris Brezillon * @pid: Part ID on the AMBA PrimeCell format
12493db446aSBoris Brezillon * @nand: Chip related info for a NAND flash.
12593db446aSBoris Brezillon *
12693db446aSBoris Brezillon * @bank: Bank number for probed device.
1275b47f407SBoris Brezillon * @dev: Parent device
1285b47f407SBoris Brezillon * @mode: Access mode
12993db446aSBoris Brezillon * @clk: Clock structure for FSMC.
13093db446aSBoris Brezillon *
13193db446aSBoris Brezillon * @read_dma_chan: DMA channel for read access
13293db446aSBoris Brezillon * @write_dma_chan: DMA channel for write access to NAND
13393db446aSBoris Brezillon * @dma_access_complete: Completion structure
13493db446aSBoris Brezillon *
1355b47f407SBoris Brezillon * @dev_timings: NAND timings
1365b47f407SBoris Brezillon *
13793db446aSBoris Brezillon * @data_pa: NAND Physical port for Data.
13893db446aSBoris Brezillon * @data_va: NAND port for Data.
13993db446aSBoris Brezillon * @cmd_va: NAND port for Command.
14093db446aSBoris Brezillon * @addr_va: NAND port for Address.
1414df6ed4fSMiquel Raynal * @regs_va: Registers base address for a given bank.
14293db446aSBoris Brezillon */
14393db446aSBoris Brezillon struct fsmc_nand_data {
144ad71148cSBoris Brezillon struct nand_controller base;
14593db446aSBoris Brezillon u32 pid;
14693db446aSBoris Brezillon struct nand_chip nand;
14793db446aSBoris Brezillon
14893db446aSBoris Brezillon unsigned int bank;
14993db446aSBoris Brezillon struct device *dev;
15093db446aSBoris Brezillon enum access_mode mode;
15193db446aSBoris Brezillon struct clk *clk;
15293db446aSBoris Brezillon
15393db446aSBoris Brezillon /* DMA related objects */
15493db446aSBoris Brezillon struct dma_chan *read_dma_chan;
15593db446aSBoris Brezillon struct dma_chan *write_dma_chan;
15693db446aSBoris Brezillon struct completion dma_access_complete;
15793db446aSBoris Brezillon
15893db446aSBoris Brezillon struct fsmc_nand_timings *dev_timings;
15993db446aSBoris Brezillon
16093db446aSBoris Brezillon dma_addr_t data_pa;
16193db446aSBoris Brezillon void __iomem *data_va;
16293db446aSBoris Brezillon void __iomem *cmd_va;
16393db446aSBoris Brezillon void __iomem *addr_va;
16493db446aSBoris Brezillon void __iomem *regs_va;
16593db446aSBoris Brezillon };
16693db446aSBoris Brezillon
fsmc_ecc1_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)16793db446aSBoris Brezillon static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
16893db446aSBoris Brezillon struct mtd_oob_region *oobregion)
16993db446aSBoris Brezillon {
17093db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd);
17193db446aSBoris Brezillon
17293db446aSBoris Brezillon if (section >= chip->ecc.steps)
17393db446aSBoris Brezillon return -ERANGE;
17493db446aSBoris Brezillon
17593db446aSBoris Brezillon oobregion->offset = (section * 16) + 2;
17693db446aSBoris Brezillon oobregion->length = 3;
17793db446aSBoris Brezillon
17893db446aSBoris Brezillon return 0;
17993db446aSBoris Brezillon }
18093db446aSBoris Brezillon
fsmc_ecc1_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)18193db446aSBoris Brezillon static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
18293db446aSBoris Brezillon struct mtd_oob_region *oobregion)
18393db446aSBoris Brezillon {
18493db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd);
18593db446aSBoris Brezillon
18693db446aSBoris Brezillon if (section >= chip->ecc.steps)
18793db446aSBoris Brezillon return -ERANGE;
18893db446aSBoris Brezillon
18993db446aSBoris Brezillon oobregion->offset = (section * 16) + 8;
19093db446aSBoris Brezillon
19193db446aSBoris Brezillon if (section < chip->ecc.steps - 1)
19293db446aSBoris Brezillon oobregion->length = 8;
19393db446aSBoris Brezillon else
19493db446aSBoris Brezillon oobregion->length = mtd->oobsize - oobregion->offset;
19593db446aSBoris Brezillon
19693db446aSBoris Brezillon return 0;
19793db446aSBoris Brezillon }
19893db446aSBoris Brezillon
19993db446aSBoris Brezillon static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
20093db446aSBoris Brezillon .ecc = fsmc_ecc1_ooblayout_ecc,
20193db446aSBoris Brezillon .free = fsmc_ecc1_ooblayout_free,
20293db446aSBoris Brezillon };
20393db446aSBoris Brezillon
20493db446aSBoris Brezillon /*
20593db446aSBoris Brezillon * ECC placement definitions in oobfree type format.
20693db446aSBoris Brezillon * There are 13 bytes of ecc for every 512 byte block and it has to be read
20793db446aSBoris Brezillon * consecutively and immediately after the 512 byte data block for hardware to
20893db446aSBoris Brezillon * generate the error bit offsets in 512 byte data.
20993db446aSBoris Brezillon */
fsmc_ecc4_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)21093db446aSBoris Brezillon static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
21193db446aSBoris Brezillon struct mtd_oob_region *oobregion)
21293db446aSBoris Brezillon {
21393db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd);
21493db446aSBoris Brezillon
21593db446aSBoris Brezillon if (section >= chip->ecc.steps)
21693db446aSBoris Brezillon return -ERANGE;
21793db446aSBoris Brezillon
21893db446aSBoris Brezillon oobregion->length = chip->ecc.bytes;
21993db446aSBoris Brezillon
22093db446aSBoris Brezillon if (!section && mtd->writesize <= 512)
22193db446aSBoris Brezillon oobregion->offset = 0;
22293db446aSBoris Brezillon else
22393db446aSBoris Brezillon oobregion->offset = (section * 16) + 2;
22493db446aSBoris Brezillon
22593db446aSBoris Brezillon return 0;
22693db446aSBoris Brezillon }
22793db446aSBoris Brezillon
fsmc_ecc4_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)22893db446aSBoris Brezillon static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
22993db446aSBoris Brezillon struct mtd_oob_region *oobregion)
23093db446aSBoris Brezillon {
23193db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd);
23293db446aSBoris Brezillon
23393db446aSBoris Brezillon if (section >= chip->ecc.steps)
23493db446aSBoris Brezillon return -ERANGE;
23593db446aSBoris Brezillon
23693db446aSBoris Brezillon oobregion->offset = (section * 16) + 15;
23793db446aSBoris Brezillon
23893db446aSBoris Brezillon if (section < chip->ecc.steps - 1)
23993db446aSBoris Brezillon oobregion->length = 3;
24093db446aSBoris Brezillon else
24193db446aSBoris Brezillon oobregion->length = mtd->oobsize - oobregion->offset;
24293db446aSBoris Brezillon
24393db446aSBoris Brezillon return 0;
24493db446aSBoris Brezillon }
24593db446aSBoris Brezillon
24693db446aSBoris Brezillon static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
24793db446aSBoris Brezillon .ecc = fsmc_ecc4_ooblayout_ecc,
24893db446aSBoris Brezillon .free = fsmc_ecc4_ooblayout_free,
24993db446aSBoris Brezillon };
25093db446aSBoris Brezillon
nand_to_fsmc(struct nand_chip * chip)251bfc535f4SBoris Brezillon static inline struct fsmc_nand_data *nand_to_fsmc(struct nand_chip *chip)
25293db446aSBoris Brezillon {
253bfc535f4SBoris Brezillon return container_of(chip, struct fsmc_nand_data, nand);
25493db446aSBoris Brezillon }
25593db446aSBoris Brezillon
25693db446aSBoris Brezillon /*
25793db446aSBoris Brezillon * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
25893db446aSBoris Brezillon *
25993db446aSBoris Brezillon * This routine initializes timing parameters related to NAND memory access in
26093db446aSBoris Brezillon * FSMC registers
26193db446aSBoris Brezillon */
fsmc_nand_setup(struct fsmc_nand_data * host,struct fsmc_nand_timings * tims)26293db446aSBoris Brezillon static void fsmc_nand_setup(struct fsmc_nand_data *host,
26393db446aSBoris Brezillon struct fsmc_nand_timings *tims)
26493db446aSBoris Brezillon {
265fc43f45eSBoris Brezillon u32 value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
266fc43f45eSBoris Brezillon u32 tclr, tar, thiz, thold, twait, tset;
26793db446aSBoris Brezillon
26893db446aSBoris Brezillon tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
26993db446aSBoris Brezillon tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
27093db446aSBoris Brezillon thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
27193db446aSBoris Brezillon thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
27293db446aSBoris Brezillon twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
27393db446aSBoris Brezillon tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
27493db446aSBoris Brezillon
27593db446aSBoris Brezillon if (host->nand.options & NAND_BUSWIDTH_16)
276fc43f45eSBoris Brezillon value |= FSMC_DEVWID_16;
27793db446aSBoris Brezillon
278fc43f45eSBoris Brezillon writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC);
2794df6ed4fSMiquel Raynal writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM);
2804df6ed4fSMiquel Raynal writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB);
28193db446aSBoris Brezillon }
28293db446aSBoris Brezillon
fsmc_calc_timings(struct fsmc_nand_data * host,const struct nand_sdr_timings * sdrt,struct fsmc_nand_timings * tims)28393db446aSBoris Brezillon static int fsmc_calc_timings(struct fsmc_nand_data *host,
28493db446aSBoris Brezillon const struct nand_sdr_timings *sdrt,
28593db446aSBoris Brezillon struct fsmc_nand_timings *tims)
28693db446aSBoris Brezillon {
28793db446aSBoris Brezillon unsigned long hclk = clk_get_rate(host->clk);
28893db446aSBoris Brezillon unsigned long hclkn = NSEC_PER_SEC / hclk;
2899472335eSHerve Codina u32 thiz, thold, twait, tset, twait_min;
29093db446aSBoris Brezillon
29193db446aSBoris Brezillon if (sdrt->tRC_min < 30000)
29293db446aSBoris Brezillon return -EOPNOTSUPP;
29393db446aSBoris Brezillon
29493db446aSBoris Brezillon tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1;
29593db446aSBoris Brezillon if (tims->tar > FSMC_TAR_MASK)
29693db446aSBoris Brezillon tims->tar = FSMC_TAR_MASK;
29793db446aSBoris Brezillon tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1;
29893db446aSBoris Brezillon if (tims->tclr > FSMC_TCLR_MASK)
29993db446aSBoris Brezillon tims->tclr = FSMC_TCLR_MASK;
30093db446aSBoris Brezillon
30193db446aSBoris Brezillon thiz = sdrt->tCS_min - sdrt->tWP_min;
30293db446aSBoris Brezillon tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn);
30393db446aSBoris Brezillon
30493db446aSBoris Brezillon thold = sdrt->tDH_min;
30593db446aSBoris Brezillon if (thold < sdrt->tCH_min)
30693db446aSBoris Brezillon thold = sdrt->tCH_min;
30793db446aSBoris Brezillon if (thold < sdrt->tCLH_min)
30893db446aSBoris Brezillon thold = sdrt->tCLH_min;
30993db446aSBoris Brezillon if (thold < sdrt->tWH_min)
31093db446aSBoris Brezillon thold = sdrt->tWH_min;
31193db446aSBoris Brezillon if (thold < sdrt->tALH_min)
31293db446aSBoris Brezillon thold = sdrt->tALH_min;
31393db446aSBoris Brezillon if (thold < sdrt->tREH_min)
31493db446aSBoris Brezillon thold = sdrt->tREH_min;
31593db446aSBoris Brezillon tims->thold = DIV_ROUND_UP(thold / 1000, hclkn);
31693db446aSBoris Brezillon if (tims->thold == 0)
31793db446aSBoris Brezillon tims->thold = 1;
31893db446aSBoris Brezillon else if (tims->thold > FSMC_THOLD_MASK)
31993db446aSBoris Brezillon tims->thold = FSMC_THOLD_MASK;
32093db446aSBoris Brezillon
32193db446aSBoris Brezillon tset = max(sdrt->tCS_min - sdrt->tWP_min,
32293db446aSBoris Brezillon sdrt->tCEA_max - sdrt->tREA_max);
32393db446aSBoris Brezillon tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1;
32493db446aSBoris Brezillon if (tims->tset == 0)
32593db446aSBoris Brezillon tims->tset = 1;
32693db446aSBoris Brezillon else if (tims->tset > FSMC_TSET_MASK)
32793db446aSBoris Brezillon tims->tset = FSMC_TSET_MASK;
32893db446aSBoris Brezillon
3299472335eSHerve Codina /*
3309472335eSHerve Codina * According to SPEAr300 Reference Manual (RM0082) which gives more
3319472335eSHerve Codina * information related to FSMSC timings than the SPEAr600 one (RM0305),
3329472335eSHerve Codina * twait >= tCEA - (tset * TCLK) + TOUTDEL + TINDEL
3339472335eSHerve Codina */
3349472335eSHerve Codina twait_min = sdrt->tCEA_max - ((tims->tset + 1) * hclkn * 1000)
3359472335eSHerve Codina + TOUTDEL + TINDEL;
3369472335eSHerve Codina twait = max3(sdrt->tRP_min, sdrt->tWP_min, twait_min);
3379472335eSHerve Codina
3389472335eSHerve Codina tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1;
3399472335eSHerve Codina if (tims->twait == 0)
3409472335eSHerve Codina tims->twait = 1;
3419472335eSHerve Codina else if (tims->twait > FSMC_TWAIT_MASK)
3429472335eSHerve Codina tims->twait = FSMC_TWAIT_MASK;
3439472335eSHerve Codina
34493db446aSBoris Brezillon return 0;
34593db446aSBoris Brezillon }
34693db446aSBoris Brezillon
fsmc_setup_interface(struct nand_chip * nand,int csline,const struct nand_interface_config * conf)3474c46667bSMiquel Raynal static int fsmc_setup_interface(struct nand_chip *nand, int csline,
3484c46667bSMiquel Raynal const struct nand_interface_config *conf)
34993db446aSBoris Brezillon {
3501e809f7eSBoris Brezillon struct fsmc_nand_data *host = nand_to_fsmc(nand);
35193db446aSBoris Brezillon struct fsmc_nand_timings tims;
35293db446aSBoris Brezillon const struct nand_sdr_timings *sdrt;
35393db446aSBoris Brezillon int ret;
35493db446aSBoris Brezillon
35593db446aSBoris Brezillon sdrt = nand_get_sdr_timings(conf);
35693db446aSBoris Brezillon if (IS_ERR(sdrt))
35793db446aSBoris Brezillon return PTR_ERR(sdrt);
35893db446aSBoris Brezillon
35993db446aSBoris Brezillon ret = fsmc_calc_timings(host, sdrt, &tims);
36093db446aSBoris Brezillon if (ret)
36193db446aSBoris Brezillon return ret;
36293db446aSBoris Brezillon
36393db446aSBoris Brezillon if (csline == NAND_DATA_IFACE_CHECK_ONLY)
36493db446aSBoris Brezillon return 0;
36593db446aSBoris Brezillon
36693db446aSBoris Brezillon fsmc_nand_setup(host, &tims);
36793db446aSBoris Brezillon
36893db446aSBoris Brezillon return 0;
36993db446aSBoris Brezillon }
37093db446aSBoris Brezillon
37193db446aSBoris Brezillon /*
37293db446aSBoris Brezillon * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
37393db446aSBoris Brezillon */
fsmc_enable_hwecc(struct nand_chip * chip,int mode)374ec47636cSBoris Brezillon static void fsmc_enable_hwecc(struct nand_chip *chip, int mode)
37593db446aSBoris Brezillon {
376bfc535f4SBoris Brezillon struct fsmc_nand_data *host = nand_to_fsmc(chip);
37793db446aSBoris Brezillon
3788f3931edSBoris Brezillon writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256,
3798f3931edSBoris Brezillon host->regs_va + FSMC_PC);
3808f3931edSBoris Brezillon writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCEN,
3818f3931edSBoris Brezillon host->regs_va + FSMC_PC);
3828f3931edSBoris Brezillon writel_relaxed(readl(host->regs_va + FSMC_PC) | FSMC_ECCEN,
3838f3931edSBoris Brezillon host->regs_va + FSMC_PC);
38493db446aSBoris Brezillon }
38593db446aSBoris Brezillon
38693db446aSBoris Brezillon /*
38793db446aSBoris Brezillon * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
38893db446aSBoris Brezillon * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
38993db446aSBoris Brezillon * max of 8-bits)
39093db446aSBoris Brezillon */
fsmc_read_hwecc_ecc4(struct nand_chip * chip,const u8 * data,u8 * ecc)391fc43f45eSBoris Brezillon static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const u8 *data,
392fc43f45eSBoris Brezillon u8 *ecc)
39393db446aSBoris Brezillon {
394bfc535f4SBoris Brezillon struct fsmc_nand_data *host = nand_to_fsmc(chip);
395fc43f45eSBoris Brezillon u32 ecc_tmp;
39693db446aSBoris Brezillon unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
39793db446aSBoris Brezillon
39893db446aSBoris Brezillon do {
3994df6ed4fSMiquel Raynal if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY)
40093db446aSBoris Brezillon break;
401fc43f45eSBoris Brezillon
40293db446aSBoris Brezillon cond_resched();
40393db446aSBoris Brezillon } while (!time_after_eq(jiffies, deadline));
40493db446aSBoris Brezillon
40593db446aSBoris Brezillon if (time_after_eq(jiffies, deadline)) {
40693db446aSBoris Brezillon dev_err(host->dev, "calculate ecc timed out\n");
40793db446aSBoris Brezillon return -ETIMEDOUT;
40893db446aSBoris Brezillon }
40993db446aSBoris Brezillon
4104df6ed4fSMiquel Raynal ecc_tmp = readl_relaxed(host->regs_va + ECC1);
411fc43f45eSBoris Brezillon ecc[0] = ecc_tmp;
412fc43f45eSBoris Brezillon ecc[1] = ecc_tmp >> 8;
413fc43f45eSBoris Brezillon ecc[2] = ecc_tmp >> 16;
414fc43f45eSBoris Brezillon ecc[3] = ecc_tmp >> 24;
41593db446aSBoris Brezillon
4164df6ed4fSMiquel Raynal ecc_tmp = readl_relaxed(host->regs_va + ECC2);
417fc43f45eSBoris Brezillon ecc[4] = ecc_tmp;
418fc43f45eSBoris Brezillon ecc[5] = ecc_tmp >> 8;
419fc43f45eSBoris Brezillon ecc[6] = ecc_tmp >> 16;
420fc43f45eSBoris Brezillon ecc[7] = ecc_tmp >> 24;
42193db446aSBoris Brezillon
4224df6ed4fSMiquel Raynal ecc_tmp = readl_relaxed(host->regs_va + ECC3);
423fc43f45eSBoris Brezillon ecc[8] = ecc_tmp;
424fc43f45eSBoris Brezillon ecc[9] = ecc_tmp >> 8;
425fc43f45eSBoris Brezillon ecc[10] = ecc_tmp >> 16;
426fc43f45eSBoris Brezillon ecc[11] = ecc_tmp >> 24;
42793db446aSBoris Brezillon
4284df6ed4fSMiquel Raynal ecc_tmp = readl_relaxed(host->regs_va + STS);
429fc43f45eSBoris Brezillon ecc[12] = ecc_tmp >> 16;
43093db446aSBoris Brezillon
43193db446aSBoris Brezillon return 0;
43293db446aSBoris Brezillon }
43393db446aSBoris Brezillon
43493db446aSBoris Brezillon /*
43593db446aSBoris Brezillon * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
43693db446aSBoris Brezillon * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
43793db446aSBoris Brezillon * max of 1-bit)
43893db446aSBoris Brezillon */
fsmc_read_hwecc_ecc1(struct nand_chip * chip,const u8 * data,u8 * ecc)439fc43f45eSBoris Brezillon static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const u8 *data,
440fc43f45eSBoris Brezillon u8 *ecc)
44193db446aSBoris Brezillon {
442bfc535f4SBoris Brezillon struct fsmc_nand_data *host = nand_to_fsmc(chip);
443fc43f45eSBoris Brezillon u32 ecc_tmp;
44493db446aSBoris Brezillon
4454df6ed4fSMiquel Raynal ecc_tmp = readl_relaxed(host->regs_va + ECC1);
446fc43f45eSBoris Brezillon ecc[0] = ecc_tmp;
447fc43f45eSBoris Brezillon ecc[1] = ecc_tmp >> 8;
448fc43f45eSBoris Brezillon ecc[2] = ecc_tmp >> 16;
44993db446aSBoris Brezillon
45093db446aSBoris Brezillon return 0;
45193db446aSBoris Brezillon }
45293db446aSBoris Brezillon
fsmc_correct_ecc1(struct nand_chip * chip,unsigned char * buf,unsigned char * read_ecc,unsigned char * calc_ecc)453ad9ffdceSMiquel Raynal static int fsmc_correct_ecc1(struct nand_chip *chip,
454ad9ffdceSMiquel Raynal unsigned char *buf,
455ad9ffdceSMiquel Raynal unsigned char *read_ecc,
456ad9ffdceSMiquel Raynal unsigned char *calc_ecc)
457ad9ffdceSMiquel Raynal {
4589be1446eSMiquel Raynal bool sm_order = chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER;
4599be1446eSMiquel Raynal
460ad9ffdceSMiquel Raynal return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
4619be1446eSMiquel Raynal chip->ecc.size, sm_order);
462ad9ffdceSMiquel Raynal }
463ad9ffdceSMiquel Raynal
46493db446aSBoris Brezillon /* Count the number of 0's in buff upto a max of max_bits */
count_written_bits(u8 * buff,int size,int max_bits)465fc43f45eSBoris Brezillon static int count_written_bits(u8 *buff, int size, int max_bits)
46693db446aSBoris Brezillon {
46793db446aSBoris Brezillon int k, written_bits = 0;
46893db446aSBoris Brezillon
46993db446aSBoris Brezillon for (k = 0; k < size; k++) {
47093db446aSBoris Brezillon written_bits += hweight8(~buff[k]);
47193db446aSBoris Brezillon if (written_bits > max_bits)
47293db446aSBoris Brezillon break;
47393db446aSBoris Brezillon }
47493db446aSBoris Brezillon
47593db446aSBoris Brezillon return written_bits;
47693db446aSBoris Brezillon }
47793db446aSBoris Brezillon
dma_complete(void * param)47893db446aSBoris Brezillon static void dma_complete(void *param)
47993db446aSBoris Brezillon {
48093db446aSBoris Brezillon struct fsmc_nand_data *host = param;
48193db446aSBoris Brezillon
48293db446aSBoris Brezillon complete(&host->dma_access_complete);
48393db446aSBoris Brezillon }
48493db446aSBoris Brezillon
dma_xfer(struct fsmc_nand_data * host,void * buffer,int len,enum dma_data_direction direction)48593db446aSBoris Brezillon static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
48693db446aSBoris Brezillon enum dma_data_direction direction)
48793db446aSBoris Brezillon {
48893db446aSBoris Brezillon struct dma_chan *chan;
48993db446aSBoris Brezillon struct dma_device *dma_dev;
49093db446aSBoris Brezillon struct dma_async_tx_descriptor *tx;
49193db446aSBoris Brezillon dma_addr_t dma_dst, dma_src, dma_addr;
49293db446aSBoris Brezillon dma_cookie_t cookie;
49393db446aSBoris Brezillon unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
49493db446aSBoris Brezillon int ret;
49593db446aSBoris Brezillon unsigned long time_left;
49693db446aSBoris Brezillon
49793db446aSBoris Brezillon if (direction == DMA_TO_DEVICE)
49893db446aSBoris Brezillon chan = host->write_dma_chan;
49993db446aSBoris Brezillon else if (direction == DMA_FROM_DEVICE)
50093db446aSBoris Brezillon chan = host->read_dma_chan;
50193db446aSBoris Brezillon else
50293db446aSBoris Brezillon return -EINVAL;
50393db446aSBoris Brezillon
50493db446aSBoris Brezillon dma_dev = chan->device;
50593db446aSBoris Brezillon dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
50693db446aSBoris Brezillon
50793db446aSBoris Brezillon if (direction == DMA_TO_DEVICE) {
50893db446aSBoris Brezillon dma_src = dma_addr;
50993db446aSBoris Brezillon dma_dst = host->data_pa;
51093db446aSBoris Brezillon } else {
51193db446aSBoris Brezillon dma_src = host->data_pa;
51293db446aSBoris Brezillon dma_dst = dma_addr;
51393db446aSBoris Brezillon }
51493db446aSBoris Brezillon
51593db446aSBoris Brezillon tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
51693db446aSBoris Brezillon len, flags);
51793db446aSBoris Brezillon if (!tx) {
51893db446aSBoris Brezillon dev_err(host->dev, "device_prep_dma_memcpy error\n");
51993db446aSBoris Brezillon ret = -EIO;
52093db446aSBoris Brezillon goto unmap_dma;
52193db446aSBoris Brezillon }
52293db446aSBoris Brezillon
52393db446aSBoris Brezillon tx->callback = dma_complete;
52493db446aSBoris Brezillon tx->callback_param = host;
52593db446aSBoris Brezillon cookie = tx->tx_submit(tx);
52693db446aSBoris Brezillon
52793db446aSBoris Brezillon ret = dma_submit_error(cookie);
52893db446aSBoris Brezillon if (ret) {
52993db446aSBoris Brezillon dev_err(host->dev, "dma_submit_error %d\n", cookie);
53093db446aSBoris Brezillon goto unmap_dma;
53193db446aSBoris Brezillon }
53293db446aSBoris Brezillon
53393db446aSBoris Brezillon dma_async_issue_pending(chan);
53493db446aSBoris Brezillon
53593db446aSBoris Brezillon time_left =
53693db446aSBoris Brezillon wait_for_completion_timeout(&host->dma_access_complete,
53793db446aSBoris Brezillon msecs_to_jiffies(3000));
53893db446aSBoris Brezillon if (time_left == 0) {
53993db446aSBoris Brezillon dmaengine_terminate_all(chan);
54093db446aSBoris Brezillon dev_err(host->dev, "wait_for_completion_timeout\n");
54193db446aSBoris Brezillon ret = -ETIMEDOUT;
54293db446aSBoris Brezillon goto unmap_dma;
54393db446aSBoris Brezillon }
54493db446aSBoris Brezillon
54593db446aSBoris Brezillon ret = 0;
54693db446aSBoris Brezillon
54793db446aSBoris Brezillon unmap_dma:
54893db446aSBoris Brezillon dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
54993db446aSBoris Brezillon
55093db446aSBoris Brezillon return ret;
55193db446aSBoris Brezillon }
55293db446aSBoris Brezillon
55393db446aSBoris Brezillon /*
55493db446aSBoris Brezillon * fsmc_write_buf - write buffer to chip
555bfc535f4SBoris Brezillon * @host: FSMC NAND controller
55693db446aSBoris Brezillon * @buf: data buffer
55793db446aSBoris Brezillon * @len: number of bytes to write
55893db446aSBoris Brezillon */
fsmc_write_buf(struct fsmc_nand_data * host,const u8 * buf,int len)559fc43f45eSBoris Brezillon static void fsmc_write_buf(struct fsmc_nand_data *host, const u8 *buf,
560bfc535f4SBoris Brezillon int len)
56193db446aSBoris Brezillon {
56293db446aSBoris Brezillon int i;
56393db446aSBoris Brezillon
564fc43f45eSBoris Brezillon if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
565fc43f45eSBoris Brezillon IS_ALIGNED(len, sizeof(u32))) {
566fc43f45eSBoris Brezillon u32 *p = (u32 *)buf;
567fc43f45eSBoris Brezillon
56893db446aSBoris Brezillon len = len >> 2;
56993db446aSBoris Brezillon for (i = 0; i < len; i++)
5704df6ed4fSMiquel Raynal writel_relaxed(p[i], host->data_va);
57193db446aSBoris Brezillon } else {
57293db446aSBoris Brezillon for (i = 0; i < len; i++)
5734df6ed4fSMiquel Raynal writeb_relaxed(buf[i], host->data_va);
57493db446aSBoris Brezillon }
57593db446aSBoris Brezillon }
57693db446aSBoris Brezillon
57793db446aSBoris Brezillon /*
57893db446aSBoris Brezillon * fsmc_read_buf - read chip data into buffer
579bfc535f4SBoris Brezillon * @host: FSMC NAND controller
58093db446aSBoris Brezillon * @buf: buffer to store date
58193db446aSBoris Brezillon * @len: number of bytes to read
58293db446aSBoris Brezillon */
fsmc_read_buf(struct fsmc_nand_data * host,u8 * buf,int len)583fc43f45eSBoris Brezillon static void fsmc_read_buf(struct fsmc_nand_data *host, u8 *buf, int len)
58493db446aSBoris Brezillon {
58593db446aSBoris Brezillon int i;
58693db446aSBoris Brezillon
587fc43f45eSBoris Brezillon if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
588fc43f45eSBoris Brezillon IS_ALIGNED(len, sizeof(u32))) {
589fc43f45eSBoris Brezillon u32 *p = (u32 *)buf;
590fc43f45eSBoris Brezillon
59193db446aSBoris Brezillon len = len >> 2;
59293db446aSBoris Brezillon for (i = 0; i < len; i++)
5934df6ed4fSMiquel Raynal p[i] = readl_relaxed(host->data_va);
59493db446aSBoris Brezillon } else {
59593db446aSBoris Brezillon for (i = 0; i < len; i++)
5964df6ed4fSMiquel Raynal buf[i] = readb_relaxed(host->data_va);
59793db446aSBoris Brezillon }
59893db446aSBoris Brezillon }
59993db446aSBoris Brezillon
60093db446aSBoris Brezillon /*
60193db446aSBoris Brezillon * fsmc_read_buf_dma - read chip data into buffer
602bfc535f4SBoris Brezillon * @host: FSMC NAND controller
60393db446aSBoris Brezillon * @buf: buffer to store date
60493db446aSBoris Brezillon * @len: number of bytes to read
60593db446aSBoris Brezillon */
fsmc_read_buf_dma(struct fsmc_nand_data * host,u8 * buf,int len)606fc43f45eSBoris Brezillon static void fsmc_read_buf_dma(struct fsmc_nand_data *host, u8 *buf,
607bfc535f4SBoris Brezillon int len)
60893db446aSBoris Brezillon {
60993db446aSBoris Brezillon dma_xfer(host, buf, len, DMA_FROM_DEVICE);
61093db446aSBoris Brezillon }
61193db446aSBoris Brezillon
61293db446aSBoris Brezillon /*
61393db446aSBoris Brezillon * fsmc_write_buf_dma - write buffer to chip
614bfc535f4SBoris Brezillon * @host: FSMC NAND controller
61593db446aSBoris Brezillon * @buf: data buffer
61693db446aSBoris Brezillon * @len: number of bytes to write
61793db446aSBoris Brezillon */
fsmc_write_buf_dma(struct fsmc_nand_data * host,const u8 * buf,int len)618fc43f45eSBoris Brezillon static void fsmc_write_buf_dma(struct fsmc_nand_data *host, const u8 *buf,
61993db446aSBoris Brezillon int len)
62093db446aSBoris Brezillon {
62193db446aSBoris Brezillon dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
62293db446aSBoris Brezillon }
62393db446aSBoris Brezillon
6244da712e7SMiquel Raynal /*
6254da712e7SMiquel Raynal * fsmc_exec_op - hook called by the core to execute NAND operations
6264da712e7SMiquel Raynal *
6274da712e7SMiquel Raynal * This controller is simple enough and thus does not need to use the parser
6284da712e7SMiquel Raynal * provided by the core, instead, handle every situation here.
6294da712e7SMiquel Raynal */
fsmc_exec_op(struct nand_chip * chip,const struct nand_operation * op,bool check_only)6304da712e7SMiquel Raynal static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op,
6314da712e7SMiquel Raynal bool check_only)
6324da712e7SMiquel Raynal {
633bfc535f4SBoris Brezillon struct fsmc_nand_data *host = nand_to_fsmc(chip);
6344da712e7SMiquel Raynal const struct nand_op_instr *instr = NULL;
6354da712e7SMiquel Raynal int ret = 0;
6364da712e7SMiquel Raynal unsigned int op_id;
6374da712e7SMiquel Raynal int i;
6384da712e7SMiquel Raynal
639ce446b4bSBoris Brezillon if (check_only)
640ce446b4bSBoris Brezillon return 0;
641ce446b4bSBoris Brezillon
6424da712e7SMiquel Raynal pr_debug("Executing operation [%d instructions]:\n", op->ninstrs);
643550b9fc4SBoris Brezillon
6444da712e7SMiquel Raynal for (op_id = 0; op_id < op->ninstrs; op_id++) {
6454da712e7SMiquel Raynal instr = &op->instrs[op_id];
6464da712e7SMiquel Raynal
647bf828322SSascha Hauer nand_op_trace(" ", instr);
648bf828322SSascha Hauer
6494da712e7SMiquel Raynal switch (instr->type) {
6504da712e7SMiquel Raynal case NAND_OP_CMD_INSTR:
6514da712e7SMiquel Raynal writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va);
6524da712e7SMiquel Raynal break;
6534da712e7SMiquel Raynal
6544da712e7SMiquel Raynal case NAND_OP_ADDR_INSTR:
6554da712e7SMiquel Raynal for (i = 0; i < instr->ctx.addr.naddrs; i++)
6564da712e7SMiquel Raynal writeb_relaxed(instr->ctx.addr.addrs[i],
6574da712e7SMiquel Raynal host->addr_va);
6584da712e7SMiquel Raynal break;
6594da712e7SMiquel Raynal
6604da712e7SMiquel Raynal case NAND_OP_DATA_IN_INSTR:
6614da712e7SMiquel Raynal if (host->mode == USE_DMA_ACCESS)
662bfc535f4SBoris Brezillon fsmc_read_buf_dma(host, instr->ctx.data.buf.in,
6634da712e7SMiquel Raynal instr->ctx.data.len);
6644da712e7SMiquel Raynal else
665bfc535f4SBoris Brezillon fsmc_read_buf(host, instr->ctx.data.buf.in,
6664da712e7SMiquel Raynal instr->ctx.data.len);
6674da712e7SMiquel Raynal break;
6684da712e7SMiquel Raynal
6694da712e7SMiquel Raynal case NAND_OP_DATA_OUT_INSTR:
6704da712e7SMiquel Raynal if (host->mode == USE_DMA_ACCESS)
671fc43f45eSBoris Brezillon fsmc_write_buf_dma(host,
672fc43f45eSBoris Brezillon instr->ctx.data.buf.out,
6734da712e7SMiquel Raynal instr->ctx.data.len);
6744da712e7SMiquel Raynal else
675bfc535f4SBoris Brezillon fsmc_write_buf(host, instr->ctx.data.buf.out,
6764da712e7SMiquel Raynal instr->ctx.data.len);
6774da712e7SMiquel Raynal break;
6784da712e7SMiquel Raynal
6794da712e7SMiquel Raynal case NAND_OP_WAITRDY_INSTR:
6804da712e7SMiquel Raynal ret = nand_soft_waitrdy(chip,
6814da712e7SMiquel Raynal instr->ctx.waitrdy.timeout_ms);
6824da712e7SMiquel Raynal break;
6834da712e7SMiquel Raynal }
684a4ca0c43SHerve Codina
685a4ca0c43SHerve Codina if (instr->delay_ns)
686a4ca0c43SHerve Codina ndelay(instr->delay_ns);
6874da712e7SMiquel Raynal }
6884da712e7SMiquel Raynal
6894da712e7SMiquel Raynal return ret;
6904da712e7SMiquel Raynal }
6914da712e7SMiquel Raynal
69293db446aSBoris Brezillon /*
69393db446aSBoris Brezillon * fsmc_read_page_hwecc
69493db446aSBoris Brezillon * @chip: nand chip info structure
69593db446aSBoris Brezillon * @buf: buffer to store read data
69693db446aSBoris Brezillon * @oob_required: caller expects OOB data read to chip->oob_poi
69793db446aSBoris Brezillon * @page: page number to read
69893db446aSBoris Brezillon *
69993db446aSBoris Brezillon * This routine is needed for fsmc version 8 as reading from NAND chip has to be
70093db446aSBoris Brezillon * performed in a strict sequence as follows:
70193db446aSBoris Brezillon * data(512 byte) -> ecc(13 byte)
70293db446aSBoris Brezillon * After this read, fsmc hardware generates and reports error data bits(up to a
70393db446aSBoris Brezillon * max of 8 bits)
70493db446aSBoris Brezillon */
fsmc_read_page_hwecc(struct nand_chip * chip,u8 * buf,int oob_required,int page)705fc43f45eSBoris Brezillon static int fsmc_read_page_hwecc(struct nand_chip *chip, u8 *buf,
706b9761687SBoris Brezillon int oob_required, int page)
70793db446aSBoris Brezillon {
708b9761687SBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip);
70993db446aSBoris Brezillon int i, j, s, stat, eccsize = chip->ecc.size;
71093db446aSBoris Brezillon int eccbytes = chip->ecc.bytes;
71193db446aSBoris Brezillon int eccsteps = chip->ecc.steps;
712fc43f45eSBoris Brezillon u8 *p = buf;
713fc43f45eSBoris Brezillon u8 *ecc_calc = chip->ecc.calc_buf;
714fc43f45eSBoris Brezillon u8 *ecc_code = chip->ecc.code_buf;
71541d6f0d0SGustavo A. R. Silva int off, len, ret, group = 0;
71693db446aSBoris Brezillon /*
717fc43f45eSBoris Brezillon * ecc_oob is intentionally taken as u16. In 16bit devices, we
71893db446aSBoris Brezillon * end up reading 14 bytes (7 words) from oob. The local array is
71993db446aSBoris Brezillon * to maintain word alignment
72093db446aSBoris Brezillon */
721fc43f45eSBoris Brezillon u16 ecc_oob[7];
722fc43f45eSBoris Brezillon u8 *oob = (u8 *)&ecc_oob[0];
72393db446aSBoris Brezillon unsigned int max_bitflips = 0;
72493db446aSBoris Brezillon
72593db446aSBoris Brezillon for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
72693db446aSBoris Brezillon nand_read_page_op(chip, page, s * eccsize, NULL, 0);
727ec47636cSBoris Brezillon chip->ecc.hwctl(chip, NAND_ECC_READ);
728b451f5beSMiquel Raynal ret = nand_read_data_op(chip, p, eccsize, false, false);
72941d6f0d0SGustavo A. R. Silva if (ret)
73041d6f0d0SGustavo A. R. Silva return ret;
73193db446aSBoris Brezillon
73293db446aSBoris Brezillon for (j = 0; j < eccbytes;) {
73393db446aSBoris Brezillon struct mtd_oob_region oobregion;
73493db446aSBoris Brezillon
73593db446aSBoris Brezillon ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
73693db446aSBoris Brezillon if (ret)
73793db446aSBoris Brezillon return ret;
73893db446aSBoris Brezillon
73993db446aSBoris Brezillon off = oobregion.offset;
74093db446aSBoris Brezillon len = oobregion.length;
74193db446aSBoris Brezillon
74293db446aSBoris Brezillon /*
74393db446aSBoris Brezillon * length is intentionally kept a higher multiple of 2
74493db446aSBoris Brezillon * to read at least 13 bytes even in case of 16 bit NAND
74593db446aSBoris Brezillon * devices
74693db446aSBoris Brezillon */
74793db446aSBoris Brezillon if (chip->options & NAND_BUSWIDTH_16)
74893db446aSBoris Brezillon len = roundup(len, 2);
74993db446aSBoris Brezillon
75093db446aSBoris Brezillon nand_read_oob_op(chip, page, off, oob + j, len);
75193db446aSBoris Brezillon j += len;
75293db446aSBoris Brezillon }
75393db446aSBoris Brezillon
75493db446aSBoris Brezillon memcpy(&ecc_code[i], oob, chip->ecc.bytes);
755af37d2c3SBoris Brezillon chip->ecc.calculate(chip, p, &ecc_calc[i]);
75693db446aSBoris Brezillon
75700da2ea9SBoris Brezillon stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
75893db446aSBoris Brezillon if (stat < 0) {
75993db446aSBoris Brezillon mtd->ecc_stats.failed++;
76093db446aSBoris Brezillon } else {
76193db446aSBoris Brezillon mtd->ecc_stats.corrected += stat;
76293db446aSBoris Brezillon max_bitflips = max_t(unsigned int, max_bitflips, stat);
76393db446aSBoris Brezillon }
76493db446aSBoris Brezillon }
76593db446aSBoris Brezillon
76693db446aSBoris Brezillon return max_bitflips;
76793db446aSBoris Brezillon }
76893db446aSBoris Brezillon
76993db446aSBoris Brezillon /*
77093db446aSBoris Brezillon * fsmc_bch8_correct_data
77193db446aSBoris Brezillon * @mtd: mtd info structure
77293db446aSBoris Brezillon * @dat: buffer of read data
77393db446aSBoris Brezillon * @read_ecc: ecc read from device spare area
77493db446aSBoris Brezillon * @calc_ecc: ecc calculated from read data
77593db446aSBoris Brezillon *
77693db446aSBoris Brezillon * calc_ecc is a 104 bit information containing maximum of 8 error
777fc43f45eSBoris Brezillon * offset information of 13 bits each in 512 bytes of read data.
77893db446aSBoris Brezillon */
fsmc_bch8_correct_data(struct nand_chip * chip,u8 * dat,u8 * read_ecc,u8 * calc_ecc)779fc43f45eSBoris Brezillon static int fsmc_bch8_correct_data(struct nand_chip *chip, u8 *dat,
780fc43f45eSBoris Brezillon u8 *read_ecc, u8 *calc_ecc)
78193db446aSBoris Brezillon {
782bfc535f4SBoris Brezillon struct fsmc_nand_data *host = nand_to_fsmc(chip);
783fc43f45eSBoris Brezillon u32 err_idx[8];
784fc43f45eSBoris Brezillon u32 num_err, i;
785fc43f45eSBoris Brezillon u32 ecc1, ecc2, ecc3, ecc4;
78693db446aSBoris Brezillon
7874df6ed4fSMiquel Raynal num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF;
78893db446aSBoris Brezillon
78993db446aSBoris Brezillon /* no bit flipping */
79093db446aSBoris Brezillon if (likely(num_err == 0))
79193db446aSBoris Brezillon return 0;
79293db446aSBoris Brezillon
79393db446aSBoris Brezillon /* too many errors */
79493db446aSBoris Brezillon if (unlikely(num_err > 8)) {
79593db446aSBoris Brezillon /*
79693db446aSBoris Brezillon * This is a temporary erase check. A newly erased page read
79793db446aSBoris Brezillon * would result in an ecc error because the oob data is also
79893db446aSBoris Brezillon * erased to FF and the calculated ecc for an FF data is not
79993db446aSBoris Brezillon * FF..FF.
80093db446aSBoris Brezillon * This is a workaround to skip performing correction in case
80193db446aSBoris Brezillon * data is FF..FF
80293db446aSBoris Brezillon *
80393db446aSBoris Brezillon * Logic:
80493db446aSBoris Brezillon * For every page, each bit written as 0 is counted until these
80593db446aSBoris Brezillon * number of bits are greater than 8 (the maximum correction
80693db446aSBoris Brezillon * capability of FSMC for each 512 + 13 bytes)
80793db446aSBoris Brezillon */
80893db446aSBoris Brezillon
80993db446aSBoris Brezillon int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
81093db446aSBoris Brezillon int bits_data = count_written_bits(dat, chip->ecc.size, 8);
81193db446aSBoris Brezillon
81293db446aSBoris Brezillon if ((bits_ecc + bits_data) <= 8) {
81393db446aSBoris Brezillon if (bits_data)
81493db446aSBoris Brezillon memset(dat, 0xff, chip->ecc.size);
81593db446aSBoris Brezillon return bits_data;
81693db446aSBoris Brezillon }
81793db446aSBoris Brezillon
81893db446aSBoris Brezillon return -EBADMSG;
81993db446aSBoris Brezillon }
82093db446aSBoris Brezillon
82193db446aSBoris Brezillon /*
82293db446aSBoris Brezillon * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
82393db446aSBoris Brezillon * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
82493db446aSBoris Brezillon *
82593db446aSBoris Brezillon * calc_ecc is a 104 bit information containing maximum of 8 error
826fc43f45eSBoris Brezillon * offset information of 13 bits each. calc_ecc is copied into a
827fc43f45eSBoris Brezillon * u64 array and error offset indexes are populated in err_idx
82893db446aSBoris Brezillon * array
82993db446aSBoris Brezillon */
8304df6ed4fSMiquel Raynal ecc1 = readl_relaxed(host->regs_va + ECC1);
8314df6ed4fSMiquel Raynal ecc2 = readl_relaxed(host->regs_va + ECC2);
8324df6ed4fSMiquel Raynal ecc3 = readl_relaxed(host->regs_va + ECC3);
8334df6ed4fSMiquel Raynal ecc4 = readl_relaxed(host->regs_va + STS);
83493db446aSBoris Brezillon
83593db446aSBoris Brezillon err_idx[0] = (ecc1 >> 0) & 0x1FFF;
83693db446aSBoris Brezillon err_idx[1] = (ecc1 >> 13) & 0x1FFF;
83793db446aSBoris Brezillon err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
83893db446aSBoris Brezillon err_idx[3] = (ecc2 >> 7) & 0x1FFF;
83993db446aSBoris Brezillon err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
84093db446aSBoris Brezillon err_idx[5] = (ecc3 >> 1) & 0x1FFF;
84193db446aSBoris Brezillon err_idx[6] = (ecc3 >> 14) & 0x1FFF;
84293db446aSBoris Brezillon err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
84393db446aSBoris Brezillon
84493db446aSBoris Brezillon i = 0;
84593db446aSBoris Brezillon while (num_err--) {
8467c26e6efSFenghua Yu err_idx[i] ^= 3;
84793db446aSBoris Brezillon
84893db446aSBoris Brezillon if (err_idx[i] < chip->ecc.size * 8) {
8497c26e6efSFenghua Yu int err = err_idx[i];
8507c26e6efSFenghua Yu
8517c26e6efSFenghua Yu dat[err >> 3] ^= BIT(err & 7);
85293db446aSBoris Brezillon i++;
85393db446aSBoris Brezillon }
85493db446aSBoris Brezillon }
85593db446aSBoris Brezillon return i;
85693db446aSBoris Brezillon }
85793db446aSBoris Brezillon
filter(struct dma_chan * chan,void * slave)85893db446aSBoris Brezillon static bool filter(struct dma_chan *chan, void *slave)
85993db446aSBoris Brezillon {
86093db446aSBoris Brezillon chan->private = slave;
86193db446aSBoris Brezillon return true;
86293db446aSBoris Brezillon }
86393db446aSBoris Brezillon
fsmc_nand_probe_config_dt(struct platform_device * pdev,struct fsmc_nand_data * host,struct nand_chip * nand)86493db446aSBoris Brezillon static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
86593db446aSBoris Brezillon struct fsmc_nand_data *host,
86693db446aSBoris Brezillon struct nand_chip *nand)
86793db446aSBoris Brezillon {
86893db446aSBoris Brezillon struct device_node *np = pdev->dev.of_node;
86993db446aSBoris Brezillon u32 val;
87093db446aSBoris Brezillon int ret;
87193db446aSBoris Brezillon
87293db446aSBoris Brezillon nand->options = 0;
87393db446aSBoris Brezillon
87493db446aSBoris Brezillon if (!of_property_read_u32(np, "bank-width", &val)) {
87593db446aSBoris Brezillon if (val == 2) {
87693db446aSBoris Brezillon nand->options |= NAND_BUSWIDTH_16;
87793db446aSBoris Brezillon } else if (val != 1) {
87893db446aSBoris Brezillon dev_err(&pdev->dev, "invalid bank-width %u\n", val);
87993db446aSBoris Brezillon return -EINVAL;
88093db446aSBoris Brezillon }
88193db446aSBoris Brezillon }
88293db446aSBoris Brezillon
88357150c40SRob Herring if (of_property_read_bool(np, "nand-skip-bbtscan"))
88493db446aSBoris Brezillon nand->options |= NAND_SKIP_BBTSCAN;
88593db446aSBoris Brezillon
88693db446aSBoris Brezillon host->dev_timings = devm_kzalloc(&pdev->dev,
887fc43f45eSBoris Brezillon sizeof(*host->dev_timings),
888fc43f45eSBoris Brezillon GFP_KERNEL);
88993db446aSBoris Brezillon if (!host->dev_timings)
89093db446aSBoris Brezillon return -ENOMEM;
891fc43f45eSBoris Brezillon
89293db446aSBoris Brezillon ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
89393db446aSBoris Brezillon sizeof(*host->dev_timings));
89493db446aSBoris Brezillon if (ret)
89593db446aSBoris Brezillon host->dev_timings = NULL;
89693db446aSBoris Brezillon
89793db446aSBoris Brezillon /* Set default NAND bank to 0 */
89893db446aSBoris Brezillon host->bank = 0;
89993db446aSBoris Brezillon if (!of_property_read_u32(np, "bank", &val)) {
90093db446aSBoris Brezillon if (val > 3) {
90193db446aSBoris Brezillon dev_err(&pdev->dev, "invalid bank %u\n", val);
90293db446aSBoris Brezillon return -EINVAL;
90393db446aSBoris Brezillon }
90493db446aSBoris Brezillon host->bank = val;
90593db446aSBoris Brezillon }
90693db446aSBoris Brezillon return 0;
90793db446aSBoris Brezillon }
90893db446aSBoris Brezillon
fsmc_nand_attach_chip(struct nand_chip * nand)9093bbddfa3SMiquel Raynal static int fsmc_nand_attach_chip(struct nand_chip *nand)
9103bbddfa3SMiquel Raynal {
9113bbddfa3SMiquel Raynal struct mtd_info *mtd = nand_to_mtd(nand);
912bfc535f4SBoris Brezillon struct fsmc_nand_data *host = nand_to_fsmc(nand);
9133bbddfa3SMiquel Raynal
91498591a68SMiquel Raynal if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
91598591a68SMiquel Raynal nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
91698591a68SMiquel Raynal
91798591a68SMiquel Raynal if (!nand->ecc.size)
91898591a68SMiquel Raynal nand->ecc.size = 512;
91998591a68SMiquel Raynal
92098591a68SMiquel Raynal if (AMBA_REV_BITS(host->pid) >= 8) {
92198591a68SMiquel Raynal nand->ecc.read_page = fsmc_read_page_hwecc;
92298591a68SMiquel Raynal nand->ecc.calculate = fsmc_read_hwecc_ecc4;
92398591a68SMiquel Raynal nand->ecc.correct = fsmc_bch8_correct_data;
92498591a68SMiquel Raynal nand->ecc.bytes = 13;
92598591a68SMiquel Raynal nand->ecc.strength = 8;
92698591a68SMiquel Raynal }
92798591a68SMiquel Raynal
9283bbddfa3SMiquel Raynal if (AMBA_REV_BITS(host->pid) >= 8) {
9293bbddfa3SMiquel Raynal switch (mtd->oobsize) {
9303bbddfa3SMiquel Raynal case 16:
9313bbddfa3SMiquel Raynal case 64:
9323bbddfa3SMiquel Raynal case 128:
9333bbddfa3SMiquel Raynal case 224:
9343bbddfa3SMiquel Raynal case 256:
9353bbddfa3SMiquel Raynal break;
9363bbddfa3SMiquel Raynal default:
9373bbddfa3SMiquel Raynal dev_warn(host->dev,
9383bbddfa3SMiquel Raynal "No oob scheme defined for oobsize %d\n",
9393bbddfa3SMiquel Raynal mtd->oobsize);
9403bbddfa3SMiquel Raynal return -EINVAL;
9413bbddfa3SMiquel Raynal }
9423bbddfa3SMiquel Raynal
9433bbddfa3SMiquel Raynal mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
9443bbddfa3SMiquel Raynal
9453bbddfa3SMiquel Raynal return 0;
9463bbddfa3SMiquel Raynal }
9473bbddfa3SMiquel Raynal
948bace41f8SMiquel Raynal switch (nand->ecc.engine_type) {
949bace41f8SMiquel Raynal case NAND_ECC_ENGINE_TYPE_ON_HOST:
9503bbddfa3SMiquel Raynal dev_info(host->dev, "Using 1-bit HW ECC scheme\n");
9513bbddfa3SMiquel Raynal nand->ecc.calculate = fsmc_read_hwecc_ecc1;
952ad9ffdceSMiquel Raynal nand->ecc.correct = fsmc_correct_ecc1;
95398591a68SMiquel Raynal nand->ecc.hwctl = fsmc_enable_hwecc;
9543bbddfa3SMiquel Raynal nand->ecc.bytes = 3;
9553bbddfa3SMiquel Raynal nand->ecc.strength = 1;
956309600c1SBoris Brezillon nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
9573bbddfa3SMiquel Raynal break;
9583bbddfa3SMiquel Raynal
959bace41f8SMiquel Raynal case NAND_ECC_ENGINE_TYPE_SOFT:
960e0a564aeSMiquel Raynal if (nand->ecc.algo == NAND_ECC_ALGO_BCH) {
9613bbddfa3SMiquel Raynal dev_info(host->dev,
9623bbddfa3SMiquel Raynal "Using 4-bit SW BCH ECC scheme\n");
9633bbddfa3SMiquel Raynal break;
9643bbddfa3SMiquel Raynal }
965fe1bc21fSGustavo A. R. Silva break;
9663bbddfa3SMiquel Raynal
967bace41f8SMiquel Raynal case NAND_ECC_ENGINE_TYPE_ON_DIE:
9683bbddfa3SMiquel Raynal break;
9693bbddfa3SMiquel Raynal
9703bbddfa3SMiquel Raynal default:
9713bbddfa3SMiquel Raynal dev_err(host->dev, "Unsupported ECC mode!\n");
9723bbddfa3SMiquel Raynal return -ENOTSUPP;
9733bbddfa3SMiquel Raynal }
9743bbddfa3SMiquel Raynal
9753bbddfa3SMiquel Raynal /*
9763bbddfa3SMiquel Raynal * Don't set layout for BCH4 SW ECC. This will be
9773c0fe36aSMiquel Raynal * generated later during BCH initialization.
9783bbddfa3SMiquel Raynal */
979bace41f8SMiquel Raynal if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
9803bbddfa3SMiquel Raynal switch (mtd->oobsize) {
9813bbddfa3SMiquel Raynal case 16:
9823bbddfa3SMiquel Raynal case 64:
9833bbddfa3SMiquel Raynal case 128:
9843bbddfa3SMiquel Raynal mtd_set_ooblayout(mtd,
9853bbddfa3SMiquel Raynal &fsmc_ecc1_ooblayout_ops);
9863bbddfa3SMiquel Raynal break;
9873bbddfa3SMiquel Raynal default:
9883bbddfa3SMiquel Raynal dev_warn(host->dev,
9893bbddfa3SMiquel Raynal "No oob scheme defined for oobsize %d\n",
9903bbddfa3SMiquel Raynal mtd->oobsize);
9913bbddfa3SMiquel Raynal return -EINVAL;
9923bbddfa3SMiquel Raynal }
9933bbddfa3SMiquel Raynal }
9943bbddfa3SMiquel Raynal
9953bbddfa3SMiquel Raynal return 0;
9963bbddfa3SMiquel Raynal }
9973bbddfa3SMiquel Raynal
9983bbddfa3SMiquel Raynal static const struct nand_controller_ops fsmc_nand_controller_ops = {
9993bbddfa3SMiquel Raynal .attach_chip = fsmc_nand_attach_chip,
1000f2abfeb2SBoris Brezillon .exec_op = fsmc_exec_op,
10014c46667bSMiquel Raynal .setup_interface = fsmc_setup_interface,
10023bbddfa3SMiquel Raynal };
10033bbddfa3SMiquel Raynal
1004ab3ab7b6SLinus Walleij /**
1005ab3ab7b6SLinus Walleij * fsmc_nand_disable() - Disables the NAND bank
1006ab3ab7b6SLinus Walleij * @host: The instance to disable
1007ab3ab7b6SLinus Walleij */
fsmc_nand_disable(struct fsmc_nand_data * host)1008ab3ab7b6SLinus Walleij static void fsmc_nand_disable(struct fsmc_nand_data *host)
1009ab3ab7b6SLinus Walleij {
1010ab3ab7b6SLinus Walleij u32 val;
1011ab3ab7b6SLinus Walleij
1012ab3ab7b6SLinus Walleij val = readl(host->regs_va + FSMC_PC);
1013ab3ab7b6SLinus Walleij val &= ~FSMC_ENABLE;
1014ab3ab7b6SLinus Walleij writel(val, host->regs_va + FSMC_PC);
1015ab3ab7b6SLinus Walleij }
1016ab3ab7b6SLinus Walleij
101793db446aSBoris Brezillon /*
101893db446aSBoris Brezillon * fsmc_nand_probe - Probe function
101993db446aSBoris Brezillon * @pdev: platform device structure
102093db446aSBoris Brezillon */
fsmc_nand_probe(struct platform_device * pdev)102193db446aSBoris Brezillon static int __init fsmc_nand_probe(struct platform_device *pdev)
102293db446aSBoris Brezillon {
102393db446aSBoris Brezillon struct fsmc_nand_data *host;
102493db446aSBoris Brezillon struct mtd_info *mtd;
102593db446aSBoris Brezillon struct nand_chip *nand;
102693db446aSBoris Brezillon struct resource *res;
10274df6ed4fSMiquel Raynal void __iomem *base;
102893db446aSBoris Brezillon dma_cap_mask_t mask;
102993db446aSBoris Brezillon int ret = 0;
103093db446aSBoris Brezillon u32 pid;
103193db446aSBoris Brezillon int i;
103293db446aSBoris Brezillon
103393db446aSBoris Brezillon /* Allocate memory for the device structure (and zero it) */
103493db446aSBoris Brezillon host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
103593db446aSBoris Brezillon if (!host)
103693db446aSBoris Brezillon return -ENOMEM;
103793db446aSBoris Brezillon
103893db446aSBoris Brezillon nand = &host->nand;
103993db446aSBoris Brezillon
104093db446aSBoris Brezillon ret = fsmc_nand_probe_config_dt(pdev, host, nand);
104193db446aSBoris Brezillon if (ret)
104293db446aSBoris Brezillon return ret;
104393db446aSBoris Brezillon
104493db446aSBoris Brezillon res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
104593db446aSBoris Brezillon host->data_va = devm_ioremap_resource(&pdev->dev, res);
104693db446aSBoris Brezillon if (IS_ERR(host->data_va))
104793db446aSBoris Brezillon return PTR_ERR(host->data_va);
104893db446aSBoris Brezillon
104993db446aSBoris Brezillon host->data_pa = (dma_addr_t)res->start;
105093db446aSBoris Brezillon
105193db446aSBoris Brezillon res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
105293db446aSBoris Brezillon host->addr_va = devm_ioremap_resource(&pdev->dev, res);
105393db446aSBoris Brezillon if (IS_ERR(host->addr_va))
105493db446aSBoris Brezillon return PTR_ERR(host->addr_va);
105593db446aSBoris Brezillon
105693db446aSBoris Brezillon res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
105793db446aSBoris Brezillon host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
105893db446aSBoris Brezillon if (IS_ERR(host->cmd_va))
105993db446aSBoris Brezillon return PTR_ERR(host->cmd_va);
106093db446aSBoris Brezillon
106193db446aSBoris Brezillon res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
10624df6ed4fSMiquel Raynal base = devm_ioremap_resource(&pdev->dev, res);
10634df6ed4fSMiquel Raynal if (IS_ERR(base))
10644df6ed4fSMiquel Raynal return PTR_ERR(base);
10654df6ed4fSMiquel Raynal
10664df6ed4fSMiquel Raynal host->regs_va = base + FSMC_NOR_REG_SIZE +
10674df6ed4fSMiquel Raynal (host->bank * FSMC_NAND_BANK_SZ);
106893db446aSBoris Brezillon
1069*ee0152d0SLi Zetao host->clk = devm_clk_get_enabled(&pdev->dev, NULL);
107093db446aSBoris Brezillon if (IS_ERR(host->clk)) {
107193db446aSBoris Brezillon dev_err(&pdev->dev, "failed to fetch block clock\n");
107293db446aSBoris Brezillon return PTR_ERR(host->clk);
107393db446aSBoris Brezillon }
107493db446aSBoris Brezillon
107593db446aSBoris Brezillon /*
107693db446aSBoris Brezillon * This device ID is actually a common AMBA ID as used on the
107793db446aSBoris Brezillon * AMBA PrimeCell bus. However it is not a PrimeCell.
107893db446aSBoris Brezillon */
107993db446aSBoris Brezillon for (pid = 0, i = 0; i < 4; i++)
1080fc43f45eSBoris Brezillon pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) &
1081fc43f45eSBoris Brezillon 255) << (i * 8);
1082fc43f45eSBoris Brezillon
108393db446aSBoris Brezillon host->pid = pid;
1084fc43f45eSBoris Brezillon
1085fc43f45eSBoris Brezillon dev_info(&pdev->dev,
1086fc43f45eSBoris Brezillon "FSMC device partno %03x, manufacturer %02x, revision %02x, config %02x\n",
108793db446aSBoris Brezillon AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
108893db446aSBoris Brezillon AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
108993db446aSBoris Brezillon
109093db446aSBoris Brezillon host->dev = &pdev->dev;
109193db446aSBoris Brezillon
109293db446aSBoris Brezillon if (host->mode == USE_DMA_ACCESS)
109393db446aSBoris Brezillon init_completion(&host->dma_access_complete);
109493db446aSBoris Brezillon
109593db446aSBoris Brezillon /* Link all private pointers */
109693db446aSBoris Brezillon mtd = nand_to_mtd(&host->nand);
109793db446aSBoris Brezillon nand_set_flash_node(nand, pdev->dev.of_node);
109893db446aSBoris Brezillon
109993db446aSBoris Brezillon mtd->dev.parent = &pdev->dev;
110093db446aSBoris Brezillon
110193db446aSBoris Brezillon nand->badblockbits = 7;
110293db446aSBoris Brezillon
11034da712e7SMiquel Raynal if (host->mode == USE_DMA_ACCESS) {
110493db446aSBoris Brezillon dma_cap_zero(mask);
110593db446aSBoris Brezillon dma_cap_set(DMA_MEMCPY, mask);
110693db446aSBoris Brezillon host->read_dma_chan = dma_request_channel(mask, filter, NULL);
110793db446aSBoris Brezillon if (!host->read_dma_chan) {
110893db446aSBoris Brezillon dev_err(&pdev->dev, "Unable to get read dma channel\n");
1109e7a97528SDan Carpenter ret = -ENODEV;
1110*ee0152d0SLi Zetao goto disable_fsmc;
111193db446aSBoris Brezillon }
111293db446aSBoris Brezillon host->write_dma_chan = dma_request_channel(mask, filter, NULL);
111393db446aSBoris Brezillon if (!host->write_dma_chan) {
111493db446aSBoris Brezillon dev_err(&pdev->dev, "Unable to get write dma channel\n");
1115e7a97528SDan Carpenter ret = -ENODEV;
111643fab011SMiquel Raynal goto release_dma_read_chan;
111793db446aSBoris Brezillon }
111893db446aSBoris Brezillon }
111993db446aSBoris Brezillon
11207a08dbaeSBoris Brezillon if (host->dev_timings) {
112193db446aSBoris Brezillon fsmc_nand_setup(host, host->dev_timings);
11227a08dbaeSBoris Brezillon nand->options |= NAND_KEEP_TIMINGS;
11237a08dbaeSBoris Brezillon }
112493db446aSBoris Brezillon
1125ad71148cSBoris Brezillon nand_controller_init(&host->base);
1126ad71148cSBoris Brezillon host->base.ops = &fsmc_nand_controller_ops;
1127ad71148cSBoris Brezillon nand->controller = &host->base;
1128ad71148cSBoris Brezillon
112993db446aSBoris Brezillon /*
113093db446aSBoris Brezillon * Scan to find existence of the device
113193db446aSBoris Brezillon */
113200ad378fSBoris Brezillon ret = nand_scan(nand, 1);
113393db446aSBoris Brezillon if (ret)
113443fab011SMiquel Raynal goto release_dma_write_chan;
113593db446aSBoris Brezillon
113693db446aSBoris Brezillon mtd->name = "nand";
113793db446aSBoris Brezillon ret = mtd_device_register(mtd, NULL, 0);
113893db446aSBoris Brezillon if (ret)
1139682cae27SMiquel Raynal goto cleanup_nand;
114093db446aSBoris Brezillon
114193db446aSBoris Brezillon platform_set_drvdata(pdev, host);
114293db446aSBoris Brezillon dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
114343fab011SMiquel Raynal
114493db446aSBoris Brezillon return 0;
114593db446aSBoris Brezillon
1146682cae27SMiquel Raynal cleanup_nand:
1147682cae27SMiquel Raynal nand_cleanup(nand);
114843fab011SMiquel Raynal release_dma_write_chan:
114993db446aSBoris Brezillon if (host->mode == USE_DMA_ACCESS)
115093db446aSBoris Brezillon dma_release_channel(host->write_dma_chan);
115143fab011SMiquel Raynal release_dma_read_chan:
115293db446aSBoris Brezillon if (host->mode == USE_DMA_ACCESS)
115393db446aSBoris Brezillon dma_release_channel(host->read_dma_chan);
1154*ee0152d0SLi Zetao disable_fsmc:
1155ab3ab7b6SLinus Walleij fsmc_nand_disable(host);
115643fab011SMiquel Raynal
115793db446aSBoris Brezillon return ret;
115893db446aSBoris Brezillon }
115993db446aSBoris Brezillon
116093db446aSBoris Brezillon /*
116193db446aSBoris Brezillon * Clean up routine
116293db446aSBoris Brezillon */
fsmc_nand_remove(struct platform_device * pdev)1163ec185b18SUwe Kleine-König static void fsmc_nand_remove(struct platform_device *pdev)
116493db446aSBoris Brezillon {
116593db446aSBoris Brezillon struct fsmc_nand_data *host = platform_get_drvdata(pdev);
116693db446aSBoris Brezillon
116793db446aSBoris Brezillon if (host) {
11689cc02f4cSMiquel Raynal struct nand_chip *chip = &host->nand;
11699cc02f4cSMiquel Raynal int ret;
11709cc02f4cSMiquel Raynal
11719cc02f4cSMiquel Raynal ret = mtd_device_unregister(nand_to_mtd(chip));
11729cc02f4cSMiquel Raynal WARN_ON(ret);
11739cc02f4cSMiquel Raynal nand_cleanup(chip);
1174ab3ab7b6SLinus Walleij fsmc_nand_disable(host);
117593db446aSBoris Brezillon
117693db446aSBoris Brezillon if (host->mode == USE_DMA_ACCESS) {
117793db446aSBoris Brezillon dma_release_channel(host->write_dma_chan);
117893db446aSBoris Brezillon dma_release_channel(host->read_dma_chan);
117993db446aSBoris Brezillon }
118093db446aSBoris Brezillon }
118193db446aSBoris Brezillon }
118293db446aSBoris Brezillon
118393db446aSBoris Brezillon #ifdef CONFIG_PM_SLEEP
fsmc_nand_suspend(struct device * dev)118493db446aSBoris Brezillon static int fsmc_nand_suspend(struct device *dev)
118593db446aSBoris Brezillon {
118693db446aSBoris Brezillon struct fsmc_nand_data *host = dev_get_drvdata(dev);
1187fc43f45eSBoris Brezillon
118893db446aSBoris Brezillon if (host)
118993db446aSBoris Brezillon clk_disable_unprepare(host->clk);
1190fc43f45eSBoris Brezillon
119193db446aSBoris Brezillon return 0;
119293db446aSBoris Brezillon }
119393db446aSBoris Brezillon
fsmc_nand_resume(struct device * dev)119493db446aSBoris Brezillon static int fsmc_nand_resume(struct device *dev)
119593db446aSBoris Brezillon {
119693db446aSBoris Brezillon struct fsmc_nand_data *host = dev_get_drvdata(dev);
1197a5a88125SYi Yang int ret;
1198fc43f45eSBoris Brezillon
119993db446aSBoris Brezillon if (host) {
1200a5a88125SYi Yang ret = clk_prepare_enable(host->clk);
1201a5a88125SYi Yang if (ret) {
1202a5a88125SYi Yang dev_err(dev, "failed to enable clk\n");
1203a5a88125SYi Yang return ret;
1204a5a88125SYi Yang }
120593db446aSBoris Brezillon if (host->dev_timings)
120693db446aSBoris Brezillon fsmc_nand_setup(host, host->dev_timings);
120730c72ab1SLinus Walleij nand_reset(&host->nand, 0);
120893db446aSBoris Brezillon }
1209fc43f45eSBoris Brezillon
121093db446aSBoris Brezillon return 0;
121193db446aSBoris Brezillon }
121293db446aSBoris Brezillon #endif
121393db446aSBoris Brezillon
121493db446aSBoris Brezillon static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
121593db446aSBoris Brezillon
121693db446aSBoris Brezillon static const struct of_device_id fsmc_nand_id_table[] = {
121793db446aSBoris Brezillon { .compatible = "st,spear600-fsmc-nand" },
121893db446aSBoris Brezillon { .compatible = "stericsson,fsmc-nand" },
121993db446aSBoris Brezillon {}
122093db446aSBoris Brezillon };
122193db446aSBoris Brezillon MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
122293db446aSBoris Brezillon
122393db446aSBoris Brezillon static struct platform_driver fsmc_nand_driver = {
1224ec185b18SUwe Kleine-König .remove_new = fsmc_nand_remove,
122593db446aSBoris Brezillon .driver = {
122693db446aSBoris Brezillon .name = "fsmc-nand",
122793db446aSBoris Brezillon .of_match_table = fsmc_nand_id_table,
122893db446aSBoris Brezillon .pm = &fsmc_nand_pm_ops,
122993db446aSBoris Brezillon },
123093db446aSBoris Brezillon };
123193db446aSBoris Brezillon
123293db446aSBoris Brezillon module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
123393db446aSBoris Brezillon
1234bb696344SBoris Brezillon MODULE_LICENSE("GPL v2");
123593db446aSBoris Brezillon MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
123693db446aSBoris Brezillon MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
1237