Home
last modified time | relevance | path

Searched +full:gic +full:- +full:its (Results 1 – 25 of 233) sorted by relevance

12345678910

/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
[all …]
H A Dbrcm,bcm7120-l2-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
10 - Florian Fainelli <f.fainelli@gmail.com>
14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
19 - outputs multiple interrupts signals towards its interrupt controller parent
21 - controls how some of the interrupts will be flowing, whether they will
26 - has one 32-bit enable word and one 32-bit status word
[all …]
/openbmc/linux/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.txt3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
32 The msi-map property is used to associate the devices with both the ITS
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
38 For GICv3 and GIC ITS bindings, see:
39 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.
[all …]
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
[all …]
H A Dfoundation-v8-gicv3.dtsi8 gic: interrupt-controller@2f000000 { label
9 compatible = "arm,gic-v3";
10 #interrupt-cells = <3>;
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-controller;
22 its: msi-controller@2f020000 { label
23 compatible = "arm,gic-v3-its";
24 msi-controller;
25 #msi-cells = <1>;
/openbmc/qemu/hw/intc/
H A Darm_gicv3.c33 if (prio != cs->hppi.prio) { in irqbetter()
34 return prio < cs->hppi.prio; in irqbetter()
38 * The same priority IRQ with non-maskable property should signal to in irqbetter()
41 if (nmi != cs->hppi.nmi) { in irqbetter()
49 if (irq <= cs->hppi.irq) { in irqbetter()
59 * of 32), and return a 32-bit integer which has a bit set for each in gicd_int_pending()
64 * + its ENABLE bit is set in gicd_int_pending()
65 * + the GICD enable bit for its group is set in gicd_int_pending()
66 * + its ACTIVE bit is not set (otherwise it would be Active+Pending) in gicd_int_pending()
67 * Conveniently we can bulk-calculate this with bitwise operations. in gicd_int_pending()
[all …]
/openbmc/linux/drivers/irqchip/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_IRQCHIP) += irqchip.o
4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o
5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o
8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
11 obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o
[all …]
H A Dirq-gic-v3-its-fsl-mc-msi.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
19 .name = "ITS-fMSI",
33 out_id = of_node ? of_msi_map_id(&mc_dev->dev, of_node, mc_dev->icid) : in fsl_mc_msi_domain_get_msi_id()
34 iort_msi_map_id(&mc_dev->dev, mc_dev->icid); in fsl_mc_msi_domain_get_msi_id()
47 return -EINVAL; in its_fsl_mc_msi_prepare()
50 if (!(mc_bus_dev->flags & FSL_MC_IS_DPRC)) in its_fsl_mc_msi_prepare()
51 return -EINVAL; in its_fsl_mc_msi_prepare()
54 * Set the device Id to be passed to the GIC-ITS: in its_fsl_mc_msi_prepare()
59 info->scratchpad[0].ul = fsl_mc_msi_domain_get_msi_id(msi_domain, in its_fsl_mc_msi_prepare()
[all …]
/openbmc/linux/arch/arm64/boot/dts/cavium/
H A Dthunder2-99xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (c) 2013-2016 Broadcom
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
21 #address-cells = <0x2>;
22 #size-cells = <0x0>;
28 enable-method = "psci";
[all …]
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip05.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/openbmc/qemu/include/hw/intc/
H A Darm_gicv3_its_common.h2 * ITS support for ARM GICv3
28 #define TYPE_ARM_GICV3_ITS "arm-gicv3-its"
93 * The ITS should call this when it is realized to add itself
94 * to its GIC's list of connected ITSes.
96 static inline void gicv3_add_its(GICv3State *s, DeviceState *its) in gicv3_add_its() argument
98 g_ptr_array_add(s->itslist, its); in gicv3_add_its()
102 * The ITS can use this for operations that must be performed on
103 * every ITS connected to the same GIC that it is
107 g_ptr_array_foreach(s->itslist, func, opaque); in gicv3_foreach_its()
110 #define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dlayerscape-pci.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
6 This controller derives its clocks from the Reset Configuration Word (RCW)
7 which is used to describe the PLL settings at the time of chip-reset.
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
22 "fsl,ls1043a-pcie"
[all …]
H A Dlayerscape-pcie-gen4.txt4 the common properties defined in mobiveil-pcie.txt.
7 - compatible: should contain the platform identifier such as:
8 "fsl,lx2160a-pcie"
9 - reg: base addresses and lengths of the PCIe controller register blocks.
12 - interrupts: A list of interrupt outputs of the controller. Must contain an
13 entry for each entry in the interrupt-names property.
14 - interrupt-names: It could include the following entries:
17 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
19 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
20 - dma-coherent: Indicates that the hardware IP block can ensure the coherency
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
9 gic500: interrupt-controller@1800000 {
10 compatible = "arm,gic-v3";
11 #address-cells = <2>;
12 #size-cells = <2>;
14 #interrupt-cells = <3>;
15 interrupt-controller;
24 gic_its: gic-its@18200000 {
25 compatible = "arm,gic-v3-its";
[all …]
/openbmc/linux/include/kvm/
H A Darm_vgic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 #include <linux/irqchip/arm-gic-v4.h>
28 #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
32 #define KVM_IRQCHIP_NUM_PINS (1020 - 32)
43 /* same for all guests, as depending only on the _host's_ GIC model */
45 /* type of the host GIC */
80 /* GIC system register CPU interface */
90 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
98 * Per-irq ops overriding some common behavious.
100 * Always called in non-preemptible section and the functions can use
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
[all …]
H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
[all …]
H A Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
/openbmc/qemu/docs/system/arm/
H A Dvirt.rst8 idiosyncrasies and limitations of a particular bit of real-world
16 ``virt-5.0`` machine type will behave like the ``virt`` machine from
17 the QEMU 5.0 release, and migration should work between ``virt-5.0``
18 of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
20 the non-versioned ``virt`` machine type.
27 - PCI/PCIe devices
28 - Flash memory
29 - Either one or two PL011 UARTs for the NonSecure World
30 - An RTC
31 - The fw_cfg device that allows a guest to obtain data from QEMU
[all …]
H A Dsbsa.rst1 Arm Server Base System Architecture Reference board (``sbsa-ref``)
4 The ``sbsa-ref`` board intends to look like real hardware (while the ``virt``
9 - `Base System Architecture <https://developer.arm.com/documentation/den0094/>`__ (BSA)
10 - `Server Base System Architecture <https://developer.arm.com/documentation/den0029/>`__ (SBSA)
21 The ``sbsa-ref`` board supports:
23 - A configurable number of AArch64 CPUs
24 - GIC version 3
25 - System bus AHCI controller
26 - System bus XHCI controller
27 - CDROM and hard disc on AHCI bus
[all …]
/openbmc/linux/Documentation/virt/kvm/devices/
H A Darm-vgic.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0
13 controller, requiring emulated user-space devices to inject interrupts to the
18 device and guest ITS devices, see arm-vgic-v3.txt. It is not possible to
26 KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit)
27 Base address in the guest physical address space of the GIC distributor
31 KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)
32 Base address in the guest physical address space of the GIC virtual cpu
39 -E2BIG Address outside of addressable IPA range
40 -EINVAL Incorrectly aligned address
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap810";
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
28 ap810-ap0 {
29 #address-cells = <2>;
30 #size-cells = <2>;
[all …]
/openbmc/qemu/hw/arm/
H A Dvirt-acpi-build.c5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
32 #include "qemu/error-report.h"
35 #include "hw/acpi/acpi-defs.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/acpi/aml-build.h"
49 #include "hw/pci-host/gpex.h"
53 #include "hw/platform-bus.h"
60 #include "hw/virtio/virtio-acpi.h"
72 for (i = 0; i < ms->smp.cpus; i++) { in acpi_dsdt_add_cpus()
88 aml_append(crs, aml_memory32_fixed(uart_memmap->base, in acpi_dsdt_add_uart()
[all …]
/openbmc/qemu/include/hw/arm/
H A Dvirt.h22 * + we want to present a very stripped-down minimalist platform,
25 * the kernel updates its device tree bindings and requires further
47 /* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
107 /* The concrete GIC values have to match the GIC version number */
152 bool its; member
176 DeviceState *gic; member
198 if (vms->gic_version == VIRT_GIC_VERSION_3) { in virt_redist_capacity()
203 return vms->memmap[region].size / redist_size; in virt_redist_capacity()
211 assert(vms->gic_version != VIRT_GIC_VERSION_2); in virt_gicv3_redist_region_count()
213 return (MACHINE(vms)->smp.cpus > redist0_capacity && in virt_gicv3_redist_region_count()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Darm,twd-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Watchdog
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-wdt
[all …]

12345678910