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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
H A Dfsl-ls1028a-qds-13bb.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2019-2021 NXP
8 * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
9 * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
12 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <0>;
19 slot1_sgmii: ethernet-phy@2 {
22 compatible = "ethernet-phy-ieee802.3-c45";
27 phy-handle = <&slot1_sgmii>;
[all …]
H A Dfsl-ls1028a-qds-7777.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2019-2021 NXP
8 * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
12 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 slot1_sxgmii0: ethernet-phy@0 {
22 compatible = "ethernet-phy-ieee802.3-c45";
25 slot1_sxgmii1: ethernet-phy@1 {
27 compatible = "ethernet-phy-ieee802.3-c45";
[all …]
H A Dfsl-ls2088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 /dts-v1/;
14 #include "fsl-ls2088a.dtsi"
15 #include "fsl-ls208xa-rdb.dtsi"
19 compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
22 stdout-path = "serial1:115200n8";
27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
[all …]
H A Dfsl-ls2080a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 /dts-v1/;
15 #include "fsl-ls2080a.dtsi"
16 #include "fsl-ls208xa-rdb.dtsi"
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
24 stdout-path = "serial1:115200n8";
29 phy-handle = <&mdio2_phy1>;
30 phy-connection-type = "10gbase-r";
34 phy-handle = <&mdio2_phy2>;
[all …]
H A Dfsl-lx2160a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2018-2020 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
H A Dimx8qm-mek.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 /dts-v1/;
13 compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
16 stdout-path = &lpuart0;
20 /delete-node/ cpu-map;
21 /delete-node/ cpu@100;
22 /delete-node/ cpu@101;
25 thermal-zones {
26 /delete-node/ cpu1-thermal;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Common Properties
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
[all …]
H A Dhisilicon-hip04-net.txt1 Hisilicon hip04 Ethernet Controller
3 * Ethernet controller node
6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
14 - phy-mode: see ethernet.txt [1].
17 - phy-handle: see ethernet.txt [1].
19 [1] Documentation/devicetree/bindings/net/ethernet.txt
22 * Ethernet ppe node:
[all …]
H A Dnixge.txt1 * NI XGE Ethernet controller
4 - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
5 older device trees with DMA engines co-located in the address map,
7 - reg: Address and length of the register set for the device. It contains the
8 information of registers in the same order as described by reg-names.
9 - reg-names: Should contain the reg names
11 "ctrl": MDIO and PHY control and status region
12 - interrupts: Should contain tx and rx interrupt
13 - interrupt-names: Should be "rx" and "tx"
14 - phy-mode: See ethernet.txt file in the same directory.
[all …]
H A Dbroadcom-bcm87xx.txt1 The Broadcom BCM87XX devices are a family of 10G Ethernet PHYs. They
2 have these bindings in addition to the standard PHY bindings.
5 "ethernet-phy-ieee802.3-c45"
9 - broadcom,c45-reg-init : one of more sets of 4 cells. The first cell
18 ethernet-phy@5 {
20 compatible = "broadcom,bcm8706", "ethernet-phy-ieee802.3-c45";
21 interrupt-parent = <&gpio>;
28 broadcom,c45-reg-init = <1 0xc808 0xff8f 0x70>;
H A Dbrcm,bcmgenet.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7xxx Ethernet Controller (GENET)
10 - Doug Berger <opendmb@gmail.com>
11 - Florian Fainelli <f.fainelli@gmail.com>
16 - brcm,genet-v1
17 - brcm,genet-v2
18 - brcm,genet-v3
19 - brcm,genet-v4
[all …]
H A Dmdio-mux-mmioreg.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
15 node must be a child of the memory-mapped device. The driver currently only
16 supports devices with 8, 16 or 32-bit registers.
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dorion5x-netgear-wnr854t.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include "orion5x-mv88f5181.dtsi"
11 model = "Netgear WNR854-t";
12 compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
24 stdout-path = "serial0:115200n8";
33 gpio-keys {
34 compatible = "gpio-keys";
[all …]
H A Dkirkwood-guruplug-server-plus.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6281.dtsi"
9 …compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281…
18 stdout-path = &uart0;
22 pinctrl: pin-controller@10000 {
23 pmx_led_health_r: pmx-led-health-r {
27 pmx_led_health_g: pmx-led-health-g {
31 pmx_led_wmode_r: pmx-led-wmode-r {
35 pmx_led_wmode_g: pmx-led-wmode-g {
[all …]
/openbmc/linux/arch/mips/boot/dts/cavium-octeon/
H A Dubnt_e100.dts1 // SPDX-License-Identifier: GPL-2.0-only
15 phy5: ethernet-phy@5 {
17 compatible = "ethernet-phy-ieee802.3-c22";
19 phy6: ethernet-phy@6 {
21 compatible = "ethernet-phy-ieee802.3-c22";
23 phy7: ethernet-phy@7 {
25 compatible = "ethernet-phy-ieee802.3-c22";
31 ethernet@0 {
32 phy-handle = <&phy7>;
33 rx-delay = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779f0-spider-ethernet.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Spider Ethernet sub-board
15 label = "ethernet-sub-board";
25 power-source = <1800>;
31 power-source = <1800>;
37 power-source = <1800>;
42 pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
43 pinctrl-names = "default";
46 ethernet-ports {
47 #address-cells = <1>;
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-width = <1>;
[all …]
H A Dt2080rdb.dts2 * T2080PCIe-RDB Board Device Tree Source
4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
59 ethernet@e0000 {
60 phy-handle = <&xg_aq1202_phy3>;
61 phy-connection-type = "xgmii";
64 ethernet@e2000 {
[all …]
H A Db4860qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "b4860si-pre.dtsi"
50 board-control@3,0 {
51 compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
57 ethernet@e8000 {
58 phy-handle = <&phy_sgmii_1e>;
59 phy-connection-type = "sgmii";
62 ethernet@ea000 {
63 phy-handle = <&phy_sgmii_1f>;
64 phy-connection-type = "sgmii";
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-mcbin.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-8040-mcbin.dtsi"
11 model = "Marvell 8040 MACCHIATOBin Double-shot";
12 compatible = "marvell,armada8040-mcbin-doubleshot",
13 "marvell,armada8040-mcbin", "marvell,armada8040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 phy0: ethernet-phy@0 {
21 compatible = "ethernet-phy-ieee802.3-c45";
26 phy8: ethernet-phy@8 {
27 compatible = "ethernet-phy-ieee802.3-c45";
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-ast2600-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
11 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
26 reserved-memory {
27 #address-cells = <1>;
28 #size-cells = <1>;
34 compatible = "shared-dma-pool";
41 compatible = "shared-dma-pool";
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dkirkwood-guruplug-server-plus.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6281.dtsi"
9 …compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281…
18 stdout-path = &uart0;
22 pinctrl: pin-controller@10000 {
23 pmx_led_health_r: pmx-led-health-r {
27 pmx_led_health_g: pmx-led-health-g {
31 pmx_led_wmode_r: pmx-led-wmode-r {
35 pmx_led_wmode_g: pmx-led-wmode-g {
[all …]
/openbmc/linux/arch/arm/boot/dts/moxa/
H A Dmoxart-uc7112lx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* moxart-uc7112lx.dts - Device Tree file for MOXA UC-7112-LX
7 /dts-v1/;
11 model = "MOXA UC-7112-LX";
12 compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart";
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <12000000>;
28 compatible = "numonyx,js28f128", "cfi-flash";
30 bank-width = <2>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568-fastrhino-r68s.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "rk3568-fastrhino-r66s.dtsi"
7 compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568";
15 adc-keys {
16 compatible = "adc-keys";
17 io-channels = <&saradc 0>;
18 io-channel-names = "buttons";
19 keyup-threshold-microvolt = <1800000>;
21 button-recovery {
24 press-threshold-microvolt = <1750>;
[all …]

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