bindings/net/ethernet-phy.yaml

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Common Properties
10   - Andrew Lunn <andrew@lunn.ch>
11   - Florian Fainelli <f.fainelli@gmail.com>
12   - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21       pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24     - $nodename
28     pattern: "^ethernet-phy(@[a-f0-9]+)?$"
32       - const: ethernet-phy-ieee802.3-c22
33         description: PHYs that implement IEEE802.3 clause 22
34       - const: ethernet-phy-ieee802.3-c45
35         description: PHYs that implement IEEE802.3 clause 45
36       - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
38           If the PHY reports an incorrect ID (or none at all) then the
39           compatible list may contain an entry with the correct PHY ID
41           The first group of digits is the 16 bit Phy Identifier 1
43           second group of digits is the Phy Identifier 2 register,
46       - items:
47           - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
48           - const: ethernet-phy-ieee802.3-c22
49       - items:
50           - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
51           - const: ethernet-phy-ieee802.3-c45
57       The ID number for the PHY.
62   max-speed:
64       - 10
65       - 100
66       - 1000
67       - 2500
68       - 5000
69       - 10000
70       - 20000
71       - 25000
72       - 40000
73       - 50000
74       - 56000
75       - 100000
76       - 200000
78       Maximum PHY supported speed in Mbits / seconds.
80   phy-10base-t1l-2.4vpp:
89   broken-turn-around:
92       If set, indicates the PHY device does not correctly release
99       External clock connected to the PHY. If not specified it is assumed
100       that the PHY uses a fixed crystal or an internal oscillator.
102   enet-phy-lane-swap:
105       If set, indicates the PHY will swap the TX/RX lanes to
109   enet-phy-lane-no-swap:
112       If set, indicates that PHY will disable swap of the
113       TX/RX lanes. This property allows the PHY to work correctly after
117   eee-broken-100tx:
120       Mark the corresponding energy efficient ethernet mode as
121       broken and request the ethernet to stop advertising it.
123   eee-broken-1000t:
126       Mark the corresponding energy efficient ethernet mode as
127       broken and request the ethernet to stop advertising it.
129   eee-broken-10gt:
132       Mark the corresponding energy efficient ethernet mode as
133       broken and request the ethernet to stop advertising it.
135   eee-broken-1000kx:
138       Mark the corresponding energy efficient ethernet mode as
139       broken and request the ethernet to stop advertising it.
141   eee-broken-10gkx4:
144       Mark the corresponding energy efficient ethernet mode as
145       broken and request the ethernet to stop advertising it.
147   eee-broken-10gkr:
150       Mark the corresponding energy efficient ethernet mode as
151       broken and request the ethernet to stop advertising it.
154     $ref: /schemas/types.yaml#/definitions/phandle-array
159   phy-is-integrated:
162       If set, indicates that the PHY is integrated into the same
163       physical package as the Ethernet MAC. If needed, muxers
164       should be configured to ensure the integrated PHY is
166       should be configured so that the external PHY is used.
171   reset-names:
172     const: phy
174   reset-gpios:
177       The GPIO phandle and specifier for the PHY reset signal.
179   reset-assert-us:
184   reset-deassert-us:
194   rx-internal-delay-ps:
196       RGMII Receive PHY Clock Delay defined in pico seconds.  This is used for
197       PHY's that have configurable RX internal delays.  If this property is
198       present then the PHY applies the RX delay.
200   tx-internal-delay-ps:
202       RGMII Transmit PHY Clock Delay defined in pico seconds.  This is used for
203       PHY's that have configurable TX internal delays. If this property is
204       present then the PHY applies the TX delay.
210       '#address-cells':
213       '#size-cells':
217       '^led@[a-f0-9]+$':
224               This define the LED index in the PHY or the MAC. It's really
229           - reg
236   - reg
241   - |
242     #include <dt-bindings/leds/common.h>
244     ethernet {
245         #address-cells = <1>;
246         #size-cells = <0>;
248         ethernet-phy@0 {
249             compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45";
250             interrupt-parent = <&PIC>;
255             reset-names = "phy";
256             reset-gpios = <&gpio1 4 1>;
257             reset-assert-us = <1000>;
258             reset-deassert-us = <2000>;
261                 #address-cells = <1>;
262                 #size-cells = <0>;
268                     default-state = "keep";