1*4c33cb31SAndrew Davis// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4c33cb31SAndrew Davis/*
3*4c33cb31SAndrew Davis * Device Tree fragment for LS1028A QDS board, serdes 7777
4*4c33cb31SAndrew Davis *
5*4c33cb31SAndrew Davis * Copyright 2019-2021 NXP
6*4c33cb31SAndrew Davis *
7*4c33cb31SAndrew Davis * Requires a LS1028A QDS board without lane B rework.
8*4c33cb31SAndrew Davis * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
9*4c33cb31SAndrew Davis * disabled, plugged in slot 1.
10*4c33cb31SAndrew Davis */
11*4c33cb31SAndrew Davis
12*4c33cb31SAndrew Davis/dts-v1/;
13*4c33cb31SAndrew Davis/plugin/;
14*4c33cb31SAndrew Davis
15*4c33cb31SAndrew Davis&mdio_slot1 {
16*4c33cb31SAndrew Davis	#address-cells = <1>;
17*4c33cb31SAndrew Davis	#size-cells = <0>;
18*4c33cb31SAndrew Davis
19*4c33cb31SAndrew Davis	/* 4 ports on AQR412 */
20*4c33cb31SAndrew Davis	slot1_sxgmii0: ethernet-phy@0 {
21*4c33cb31SAndrew Davis		reg = <0x0>;
22*4c33cb31SAndrew Davis		compatible = "ethernet-phy-ieee802.3-c45";
23*4c33cb31SAndrew Davis	};
24*4c33cb31SAndrew Davis
25*4c33cb31SAndrew Davis	slot1_sxgmii1: ethernet-phy@1 {
26*4c33cb31SAndrew Davis		reg = <0x1>;
27*4c33cb31SAndrew Davis		compatible = "ethernet-phy-ieee802.3-c45";
28*4c33cb31SAndrew Davis	};
29*4c33cb31SAndrew Davis
30*4c33cb31SAndrew Davis	slot1_sxgmii2: ethernet-phy@2 {
31*4c33cb31SAndrew Davis		reg = <0x2>;
32*4c33cb31SAndrew Davis		compatible = "ethernet-phy-ieee802.3-c45";
33*4c33cb31SAndrew Davis	};
34*4c33cb31SAndrew Davis
35*4c33cb31SAndrew Davis	slot1_sxgmii3: ethernet-phy@3 {
36*4c33cb31SAndrew Davis		reg = <0x3>;
37*4c33cb31SAndrew Davis		compatible = "ethernet-phy-ieee802.3-c45";
38*4c33cb31SAndrew Davis	};
39*4c33cb31SAndrew Davis};
40*4c33cb31SAndrew Davis
41*4c33cb31SAndrew Davis&mscc_felix_ports {
42*4c33cb31SAndrew Davis	port@0 {
43*4c33cb31SAndrew Davis		status = "okay";
44*4c33cb31SAndrew Davis		phy-handle = <&slot1_sxgmii0>;
45*4c33cb31SAndrew Davis		phy-mode = "2500base-x";
46*4c33cb31SAndrew Davis	};
47*4c33cb31SAndrew Davis
48*4c33cb31SAndrew Davis	port@1 {
49*4c33cb31SAndrew Davis		status = "okay";
50*4c33cb31SAndrew Davis		phy-handle = <&slot1_sxgmii1>;
51*4c33cb31SAndrew Davis		phy-mode = "2500base-x";
52*4c33cb31SAndrew Davis	};
53*4c33cb31SAndrew Davis
54*4c33cb31SAndrew Davis	port@2 {
55*4c33cb31SAndrew Davis		status = "okay";
56*4c33cb31SAndrew Davis		phy-handle = <&slot1_sxgmii2>;
57*4c33cb31SAndrew Davis		phy-mode = "2500base-x";
58*4c33cb31SAndrew Davis	};
59*4c33cb31SAndrew Davis
60*4c33cb31SAndrew Davis	port@3 {
61*4c33cb31SAndrew Davis		status = "okay";
62*4c33cb31SAndrew Davis		phy-handle = <&slot1_sxgmii3>;
63*4c33cb31SAndrew Davis		phy-mode = "2500base-x";
64*4c33cb31SAndrew Davis	};
65*4c33cb31SAndrew Davis};
66*4c33cb31SAndrew Davis
67*4c33cb31SAndrew Davis&mscc_felix {
68*4c33cb31SAndrew Davis	status = "okay";
69*4c33cb31SAndrew Davis};
70