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/openbmc/linux/drivers/dma/
H A Dmcf-edma-main.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
10 #include <linux/platform_data/dma-mcf-edma.h>
12 #include "fsl-edma-common.h"
20 struct edma_regs *regs = &mcf_edma->regs; in mcf_edma_tx_handler()
24 intmap = ioread32(regs->inth); in mcf_edma_tx_handler()
26 intmap |= ioread32(regs->intl); in mcf_edma_tx_handler()
30 for (ch = 0; ch < mcf_edma->n_chans; ch++) { in mcf_edma_tx_handler()
32 iowrite8(EDMA_MASK_CH(ch), regs->cint); in mcf_edma_tx_handler()
33 fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]); in mcf_edma_tx_handler()
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H A Dfsl-edma-main.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/dma/fsl-edma.c
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
7 * Driver for the Freescale eDMA engine with flexible channel multiplexing
8 * capability for DMA request sources. The eDMA bloc
73 unsigned int err, ch; fsl_edma_err_handler() local
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H A Dfsl-edma-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
10 #include <linux/dma-mapping.h>
14 #include "fsl-edma-common.h"
48 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
50 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler()
52 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
56 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler()
57 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler()
58 vchan_cookie_complete(&fsl_chan->edesc->vdesc); in fsl_edma_tx_chan_handler()
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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dfsl,edma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale enhanced Direct Memory Access(eDMA) Controller
10 The eDMA channels have multiplex capability by programmable
11 memory-mapped registers. channels are split into two groups, called
16 - Peng Fan <peng.fan@nxp.com>
21 - enum:
22 - fsl,vf610-edma
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/openbmc/linux/drivers/dma/dw-edma/
H A Ddw-edma-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA PCIe driver
13 #include <linux/dma/edma.h>
14 #include <linux/pci-epf.h>
18 #include "dw-edma-core.h"
40 /* eDMA registers location */
42 /* eDMA memory linked list location */
45 /* eDMA memory data location */
56 /* eDMA registers location */
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H A Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA core driver
13 #include <linux/err.h>
16 #include <linux/dma/edma.h>
17 #include <linux/dma-mapping.h>
19 #include "dw-edma-core.h"
20 #include "dw-edma-v0-core.h"
21 #include "dw-hdma-v0-core.h"
23 #include "../virt-dma.h"
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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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/openbmc/linux/drivers/ata/
H A Dsata_mv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sata_mv.c - Marvell SATA support
5 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
12 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
18 * --> Develop a low-power-consumption strategy, and implement it.
20 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
22 * --> [Experiment, Marvell value added] Is it possible to use target
23 * mode to cross-connect two Linux boxes with Marvell cards? If so,
31 * 80x1-B2 errata PCI#11:
34 * should be careful to insert those cards only onto PCI-X bus #0,
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/openbmc/u-boot/arch/arm/mach-keystone/
H A Dddr3.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2012-2014
15 #include <asm/ti-common/ti-edma3.h>
32 __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); in ddr3_init_ddrphy()
35 tmp &= ~(phy_cfg->pgcr1_mask); in ddr3_init_ddrphy()
36 tmp |= phy_cfg->pgcr1_val; in ddr3_init_ddrphy()
39 __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); in ddr3_init_ddrphy()
40 __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET); in ddr3_init_ddrphy()
41 __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET); in ddr3_init_ddrphy()
42 __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET); in ddr3_init_ddrphy()
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/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Dedma.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * EDMA Internal Memory Map
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
13 * Enhanced DMA (EDMA)
16 /* eDMA module registers */
20 u16 res1[3]; /* 0x08 - 0x0D */
22 u16 res2[3]; /* 0x10 - 0x15 */
32 u16 res3[3]; /* 0x20 - 0x25 */
34 u16 res4[3]; /* 0x28 - 0x2D */
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/openbmc/linux/arch/m68k/coldfire/
H A Ddevice.c2 * device.c -- common ColdFire SoC device support
23 #include <linux/platform_data/edma.h>
24 #include <linux/platform_data/dma-mcf-edma.h>
25 #include <linux/platform_data/mmc-esdhc-mcf.h>
99 #define FEC_NAME "enet-fec"
117 .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
154 .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
195 .end = MCFQSPI_BASE + MCFQSPI_SIZE - 1,
346 .end = MCFI2C_BASE0 + MCFI2C_SIZE0 - 1,
357 .name = "imx1-i2c",
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/openbmc/linux/drivers/dma/ti/
H A Dedma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI EDMA DMA engine driver
9 #include <linux/dma-mapping.h>
11 #include <linux/err.h>
25 #include <linux/platform_data/edma.h>
28 #include "../virt-dma.h"
42 /* Offsets for EDMA CC global channel registers and their shadows */
66 /* Offsets for EDMA CC global registers */
70 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
100 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
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H A Ddma-crossbar.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
8 #include <linux/err.h>
25 .compatible = "ti,dra7-dma-crossbar",
29 .compatible = "ti,am335x-edma-crossbar",
44 u32 dma_requests; /* number of DMA requests on eDMA */
60 writeb_relaxed(val, iomem + (63 - event % 4)); in ti_am335x_xbar_write()
71 map->mux_val, map->dma_line); in ti_am335x_xbar_free()
73 ti_am335x_xbar_write(xbar->iomem, map->dma_line, 0); in ti_am335x_xbar_free()
80 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); in ti_am335x_xbar_route_allocate()
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/openbmc/linux/arch/arm/boot/dts/nxp/vf/
H A Dvfxxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #include "vf610-pinfunc.h"
6 #include <dt-bindings/clock/vf610-clock.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/gpio/gpio.h>
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <24000000>;
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
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/openbmc/u-boot/arch/arm/dts/
H A Dls1021a.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a7";
37 compatible = "arm,cortex-a7";
45 compatible = "arm,armv7-timer";
53 compatible = "arm,cortex-a7-pmu";
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/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Dti,omap-iommu.txt4 - compatible : Should be one of,
5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
8 "ti,dra7-iommu" for DRA7xx IOMMU instances
9 - ti,hwmods : Name of the hwmod associated with the IOMMU instance
10 - reg : Address space for the configuration registers
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
19 - ti,#tlb-entries : Number of entries in the translation look-aside buffer.
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/openbmc/u-boot/board/freescale/m52277evb/
H A DREADME4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m52277evb/m52277evb.c Dram setup
13 - board/freescale/m52277evb/Makefile Makefile
14 - board/freescale/m52277evb/config.mk config make
15 - board/freescale/m52277evb/u-boot.lds Linker description
17 - arch/m68k/cpu/mcf5227x/cpu.c cpu specific code
18 - arch/m68k/cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
19 - arch/m68k/cpu/mcf5227x/interrupts.c cpu specific interrupt support
20 - arch/m68k/cpu/mcf5227x/speed.c system, flexbus, and cpu clock
21 - arch/m68k/cpu/mcf5227x/Makefile Makefile
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
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H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
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H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Drecv.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
17 #include <linux/dma-mapping.h>
21 #define SKB_CB_ATHBUF(__skb) (*((struct ath_rxbuf **)__skb->cb))
25 return sc->ps_enabled && in ath9k_check_auto_sleep()
26 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP); in ath9k_check_auto_sleep()
35 * to a sender if last desc is self-linked.
40 struct ath_hw *ah = sc->sc_ah; in ath_rx_buf_link()
45 ds = bf->bf_desc; in ath_rx_buf_link()
46 ds->ds_link = 0; /* link to null */ in ath_rx_buf_link()
47 ds->ds_data = bf->bf_buf_addr; in ath_rx_buf_link()
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/openbmc/linux/drivers/spi/
H A Dspi-fsl-lpspi.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
22 #include <linux/dma/imx-dma.h>
33 /* The maximum bytes that edma can transfer once.*/
34 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
143 { .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,},
144 { .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,},
152 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
154 if (fsl_lpspi->rx_buf) { \
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/openbmc/linux/drivers/dma/sf-pdma/
H A Dsf-pdma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * - drivers/dma/fsl-edma.c
8 * - drivers/dma/dw-edma/
9 * - drivers/dma/pxa-dma.c
12 * - Chapter 12 "Platform DMA Engine (PDMA)" of
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
21 #include <linux/dma-mapping.h>
25 #include "sf-pdma.h"
60 desc->chan = chan; in sf_pdma_alloc_desc()
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/openbmc/qemu/hw/s390x/
H A Ds390-pci-inst.c10 * your option) any later version. See the COPYING file in the top-level
17 #include "qemu/error-report.h"
20 #include "hw/s390x/s390-pci-inst.h"
21 #include "hw/s390x/s390-pci-bus.h"
22 #include "hw/s390x/s390-pci-kvm.h"
23 #include "hw/s390x/s390-pci-vfio.h"
30 if (iommu->dma_limit) { in inc_dma_avail()
31 iommu->dma_limit->avail++; in inc_dma_avail()
37 if (iommu->dma_limit) { in dec_dma_avail()
38 iommu->dma_limit->avail--; in dec_dma_avail()
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/openbmc/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
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