Lines Matching +full:edma +full:- +full:err
1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
10 #include <linux/dma-mapping.h>
14 #include "fsl-edma-common.h"
48 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
50 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler()
52 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
56 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler()
57 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler()
58 vchan_cookie_complete(&fsl_chan->edesc->vdesc); in fsl_edma_tx_chan_handler()
59 fsl_chan->edesc = NULL; in fsl_edma_tx_chan_handler()
60 fsl_chan->status = DMA_COMPLETE; in fsl_edma_tx_chan_handler()
61 fsl_chan->idle = true; in fsl_edma_tx_chan_handler()
63 vchan_cyclic_callback(&fsl_chan->edesc->vdesc); in fsl_edma_tx_chan_handler()
66 if (!fsl_chan->edesc) in fsl_edma_tx_chan_handler()
69 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
78 if (fsl_chan->is_rxchan) in fsl_edma3_enable_request()
83 if (fsl_chan->is_remote) in fsl_edma3_enable_request()
93 if (!edma_readl(fsl_chan->edma, fsl_chan->mux_addr)) in fsl_edma3_enable_request()
94 edma_writel(fsl_chan->edma, fsl_chan->srcid, fsl_chan->mux_addr); in fsl_edma3_enable_request()
104 struct edma_regs *regs = &fsl_chan->edma->regs; in fsl_edma_enable_request()
105 u32 ch = fsl_chan->vchan.chan.chan_id; in fsl_edma_enable_request()
110 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { in fsl_edma_enable_request()
111 edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); in fsl_edma_enable_request()
112 edma_writeb(fsl_chan->edma, ch, regs->serq); in fsl_edma_enable_request()
117 iowrite8(EDMA_SEEI_SEEI(ch), regs->seei); in fsl_edma_enable_request()
118 iowrite8(ch, regs->serq); in fsl_edma_enable_request()
130 edma_writel(fsl_chan->edma, 0, fsl_chan->mux_addr); in fsl_edma3_disable_request()
138 struct edma_regs *regs = &fsl_chan->edma->regs; in fsl_edma_disable_request()
139 u32 ch = fsl_chan->vchan.chan.chan_id; in fsl_edma_disable_request()
144 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) { in fsl_edma_disable_request()
145 edma_writeb(fsl_chan->edma, ch, regs->cerq); in fsl_edma_disable_request()
146 edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei); in fsl_edma_disable_request()
151 iowrite8(ch, regs->cerq); in fsl_edma_disable_request()
152 iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei); in fsl_edma_disable_request()
185 u32 ch = fsl_chan->vchan.chan.chan_id; in fsl_edma_chan_mux()
188 int endian_diff[4] = {3, 1, -1, -3}; in fsl_edma_chan_mux()
189 u32 dmamux_nr = fsl_chan->edma->drvdata->dmamuxs; in fsl_edma_chan_mux()
194 chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr; in fsl_edma_chan_mux()
195 ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux; in fsl_edma_chan_mux()
197 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_MUX_SWAP) in fsl_edma_chan_mux()
200 muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux]; in fsl_edma_chan_mux()
203 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_CONFIG32) in fsl_edma_chan_mux()
216 val = ffs(addr_width) - 1; in fsl_edma_get_tcd_attr()
226 for (i = 0; i < fsl_desc->n_tcds; i++) in fsl_edma_free_desc()
227 dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd, in fsl_edma_free_desc()
228 fsl_desc->tcd[i].ptcd); in fsl_edma_free_desc()
238 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); in fsl_edma_terminate_all()
240 fsl_chan->edesc = NULL; in fsl_edma_terminate_all()
241 fsl_chan->idle = true; in fsl_edma_terminate_all()
242 vchan_get_all_descriptors(&fsl_chan->vchan, &head); in fsl_edma_terminate_all()
243 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); in fsl_edma_terminate_all()
244 vchan_dma_desc_free_list(&fsl_chan->vchan, &head); in fsl_edma_terminate_all()
247 pm_runtime_allow(fsl_chan->pd_dev); in fsl_edma_terminate_all()
257 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); in fsl_edma_pause()
258 if (fsl_chan->edesc) { in fsl_edma_pause()
260 fsl_chan->status = DMA_PAUSED; in fsl_edma_pause()
261 fsl_chan->idle = true; in fsl_edma_pause()
263 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); in fsl_edma_pause()
272 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); in fsl_edma_resume()
273 if (fsl_chan->edesc) { in fsl_edma_resume()
275 fsl_chan->status = DMA_IN_PROGRESS; in fsl_edma_resume()
276 fsl_chan->idle = false; in fsl_edma_resume()
278 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); in fsl_edma_resume()
284 if (fsl_chan->dma_dir != DMA_NONE) in fsl_edma_unprep_slave_dma()
285 dma_unmap_resource(fsl_chan->vchan.chan.device->dev, in fsl_edma_unprep_slave_dma()
286 fsl_chan->dma_dev_addr, in fsl_edma_unprep_slave_dma()
287 fsl_chan->dma_dev_size, in fsl_edma_unprep_slave_dma()
288 fsl_chan->dma_dir, 0); in fsl_edma_unprep_slave_dma()
289 fsl_chan->dma_dir = DMA_NONE; in fsl_edma_unprep_slave_dma()
295 struct device *dev = fsl_chan->vchan.chan.device->dev; in fsl_edma_prep_slave_dma()
303 addr = fsl_chan->cfg.dst_addr; in fsl_edma_prep_slave_dma()
304 size = fsl_chan->cfg.dst_maxburst; in fsl_edma_prep_slave_dma()
308 addr = fsl_chan->cfg.src_addr; in fsl_edma_prep_slave_dma()
309 size = fsl_chan->cfg.src_maxburst; in fsl_edma_prep_slave_dma()
317 if (fsl_chan->dma_dir == dma_dir) in fsl_edma_prep_slave_dma()
322 fsl_chan->dma_dev_addr = dma_map_resource(dev, addr, size, dma_dir, 0); in fsl_edma_prep_slave_dma()
323 if (dma_mapping_error(dev, fsl_chan->dma_dev_addr)) in fsl_edma_prep_slave_dma()
325 fsl_chan->dma_dev_size = size; in fsl_edma_prep_slave_dma()
326 fsl_chan->dma_dir = dma_dir; in fsl_edma_prep_slave_dma()
336 memcpy(&fsl_chan->cfg, cfg, sizeof(*cfg)); in fsl_edma_slave_config()
345 struct fsl_edma_desc *edesc = fsl_chan->edesc; in fsl_edma_desc_residue()
346 enum dma_transfer_direction dir = edesc->dirn; in fsl_edma_desc_residue()
353 for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) { in fsl_edma_desc_residue()
354 nbytes = le32_to_cpu(edesc->tcd[i].vtcd->nbytes); in fsl_edma_desc_residue()
357 len += nbytes * le16_to_cpu(edesc->tcd[i].vtcd->biter); in fsl_edma_desc_residue()
369 for (i = 0; i < fsl_chan->edesc->n_tcds; i++) { in fsl_edma_desc_residue()
370 nbytes = le32_to_cpu(edesc->tcd[i].vtcd->nbytes); in fsl_edma_desc_residue()
374 size = nbytes * le16_to_cpu(edesc->tcd[i].vtcd->biter); in fsl_edma_desc_residue()
377 dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr); in fsl_edma_desc_residue()
379 dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr); in fsl_edma_desc_residue()
381 len -= size; in fsl_edma_desc_residue()
383 len += dma_addr + size - cur_addr; in fsl_edma_desc_residue()
404 return fsl_chan->status; in fsl_edma_tx_status()
406 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); in fsl_edma_tx_status()
407 vdesc = vchan_find_desc(&fsl_chan->vchan, cookie); in fsl_edma_tx_status()
408 if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie) in fsl_edma_tx_status()
409 txstate->residue = in fsl_edma_tx_status()
412 txstate->residue = in fsl_edma_tx_status()
415 txstate->residue = 0; in fsl_edma_tx_status()
417 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); in fsl_edma_tx_status()
419 return fsl_chan->status; in fsl_edma_tx_status()
430 * big- or little-endian obeying the eDMA engine model endian, in fsl_edma_set_tcd_regs()
435 edma_write_tcdreg(fsl_chan, tcd->saddr, saddr); in fsl_edma_set_tcd_regs()
436 edma_write_tcdreg(fsl_chan, tcd->daddr, daddr); in fsl_edma_set_tcd_regs()
438 edma_write_tcdreg(fsl_chan, tcd->attr, attr); in fsl_edma_set_tcd_regs()
439 edma_write_tcdreg(fsl_chan, tcd->soff, soff); in fsl_edma_set_tcd_regs()
441 edma_write_tcdreg(fsl_chan, tcd->nbytes, nbytes); in fsl_edma_set_tcd_regs()
442 edma_write_tcdreg(fsl_chan, tcd->slast, slast); in fsl_edma_set_tcd_regs()
444 edma_write_tcdreg(fsl_chan, tcd->citer, citer); in fsl_edma_set_tcd_regs()
445 edma_write_tcdreg(fsl_chan, tcd->biter, biter); in fsl_edma_set_tcd_regs()
446 edma_write_tcdreg(fsl_chan, tcd->doff, doff); in fsl_edma_set_tcd_regs()
448 edma_write_tcdreg(fsl_chan, tcd->dlast_sga, dlast_sga); in fsl_edma_set_tcd_regs()
450 csr = le16_to_cpu(tcd->csr); in fsl_edma_set_tcd_regs()
452 if (fsl_chan->is_sw) { in fsl_edma_set_tcd_regs()
454 tcd->csr = cpu_to_le16(csr); in fsl_edma_set_tcd_regs()
469 edma_write_tcdreg(fsl_chan, tcd->csr, csr); in fsl_edma_set_tcd_regs()
479 struct dma_slave_config *cfg = &fsl_chan->cfg; in fsl_edma_fill_tcd()
484 * eDMA hardware SGs require the TCDs to be stored in little in fsl_edma_fill_tcd()
489 tcd->saddr = cpu_to_le32(src); in fsl_edma_fill_tcd()
490 tcd->daddr = cpu_to_le32(dst); in fsl_edma_fill_tcd()
492 tcd->attr = cpu_to_le16(attr); in fsl_edma_fill_tcd()
494 tcd->soff = cpu_to_le16(soff); in fsl_edma_fill_tcd()
496 if (fsl_chan->is_multi_fifo) { in fsl_edma_fill_tcd()
498 burst = cfg->direction == DMA_DEV_TO_MEM ? in fsl_edma_fill_tcd()
499 cfg->src_maxburst : cfg->dst_maxburst; in fsl_edma_fill_tcd()
500 nbytes |= EDMA_V3_TCD_NBYTES_MLOFF(-(burst * 4)); in fsl_edma_fill_tcd()
502 if (cfg->direction == DMA_MEM_TO_DEV) { in fsl_edma_fill_tcd()
511 tcd->nbytes = cpu_to_le32(nbytes); in fsl_edma_fill_tcd()
512 tcd->slast = cpu_to_le32(slast); in fsl_edma_fill_tcd()
514 tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer)); in fsl_edma_fill_tcd()
515 tcd->doff = cpu_to_le16(doff); in fsl_edma_fill_tcd()
517 tcd->dlast_sga = cpu_to_le32(dlast_sga); in fsl_edma_fill_tcd()
519 tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter)); in fsl_edma_fill_tcd()
529 if (fsl_chan->is_rxchan) in fsl_edma_fill_tcd()
532 if (fsl_chan->is_sw) in fsl_edma_fill_tcd()
535 tcd->csr = cpu_to_le16(csr); in fsl_edma_fill_tcd()
548 fsl_desc->echan = fsl_chan; in fsl_edma_alloc_desc()
549 fsl_desc->n_tcds = sg_len; in fsl_edma_alloc_desc()
551 fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool, in fsl_edma_alloc_desc()
552 GFP_NOWAIT, &fsl_desc->tcd[i].ptcd); in fsl_edma_alloc_desc()
553 if (!fsl_desc->tcd[i].vtcd) in fsl_edma_alloc_desc()
554 goto err; in fsl_edma_alloc_desc()
558 err: in fsl_edma_alloc_desc()
559 while (--i >= 0) in fsl_edma_alloc_desc()
560 dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd, in fsl_edma_alloc_desc()
561 fsl_desc->tcd[i].ptcd); in fsl_edma_alloc_desc()
589 fsl_desc->iscyclic = true; in fsl_edma_prep_dma_cyclic()
590 fsl_desc->dirn = direction; in fsl_edma_prep_dma_cyclic()
594 fsl_chan->attr = in fsl_edma_prep_dma_cyclic()
595 fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width); in fsl_edma_prep_dma_cyclic()
596 nbytes = fsl_chan->cfg.dst_addr_width * in fsl_edma_prep_dma_cyclic()
597 fsl_chan->cfg.dst_maxburst; in fsl_edma_prep_dma_cyclic()
599 fsl_chan->attr = in fsl_edma_prep_dma_cyclic()
600 fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width); in fsl_edma_prep_dma_cyclic()
601 nbytes = fsl_chan->cfg.src_addr_width * in fsl_edma_prep_dma_cyclic()
602 fsl_chan->cfg.src_maxburst; in fsl_edma_prep_dma_cyclic()
612 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; in fsl_edma_prep_dma_cyclic()
616 dst_addr = fsl_chan->dma_dev_addr; in fsl_edma_prep_dma_cyclic()
617 soff = fsl_chan->cfg.dst_addr_width; in fsl_edma_prep_dma_cyclic()
618 doff = fsl_chan->is_multi_fifo ? 4 : 0; in fsl_edma_prep_dma_cyclic()
620 src_addr = fsl_chan->dma_dev_addr; in fsl_edma_prep_dma_cyclic()
622 soff = fsl_chan->is_multi_fifo ? 4 : 0; in fsl_edma_prep_dma_cyclic()
623 doff = fsl_chan->cfg.src_addr_width; in fsl_edma_prep_dma_cyclic()
626 src_addr = fsl_chan->cfg.src_addr; in fsl_edma_prep_dma_cyclic()
627 dst_addr = fsl_chan->cfg.dst_addr; in fsl_edma_prep_dma_cyclic()
632 fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, dst_addr, in fsl_edma_prep_dma_cyclic()
633 fsl_chan->attr, soff, nbytes, 0, iter, in fsl_edma_prep_dma_cyclic()
638 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); in fsl_edma_prep_dma_cyclic()
662 fsl_desc->iscyclic = false; in fsl_edma_prep_slave_sg()
663 fsl_desc->dirn = direction; in fsl_edma_prep_slave_sg()
666 fsl_chan->attr = in fsl_edma_prep_slave_sg()
667 fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width); in fsl_edma_prep_slave_sg()
668 nbytes = fsl_chan->cfg.dst_addr_width * in fsl_edma_prep_slave_sg()
669 fsl_chan->cfg.dst_maxburst; in fsl_edma_prep_slave_sg()
671 fsl_chan->attr = in fsl_edma_prep_slave_sg()
672 fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width); in fsl_edma_prep_slave_sg()
673 nbytes = fsl_chan->cfg.src_addr_width * in fsl_edma_prep_slave_sg()
674 fsl_chan->cfg.src_maxburst; in fsl_edma_prep_slave_sg()
680 dst_addr = fsl_chan->dma_dev_addr; in fsl_edma_prep_slave_sg()
681 soff = fsl_chan->cfg.dst_addr_width; in fsl_edma_prep_slave_sg()
684 src_addr = fsl_chan->dma_dev_addr; in fsl_edma_prep_slave_sg()
687 doff = fsl_chan->cfg.src_addr_width; in fsl_edma_prep_slave_sg()
690 src_addr = fsl_chan->cfg.src_addr; in fsl_edma_prep_slave_sg()
691 dst_addr = fsl_chan->cfg.dst_addr; in fsl_edma_prep_slave_sg()
704 fsl_chan->cfg.src_maxburst : in fsl_edma_prep_slave_sg()
705 fsl_chan->cfg.dst_maxburst; in fsl_edma_prep_slave_sg()
708 for (j = burst; j > 1; j--) { in fsl_edma_prep_slave_sg()
719 if (i < sg_len - 1) { in fsl_edma_prep_slave_sg()
720 last_sg = fsl_desc->tcd[(i + 1)].ptcd; in fsl_edma_prep_slave_sg()
721 fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, in fsl_edma_prep_slave_sg()
722 dst_addr, fsl_chan->attr, soff, in fsl_edma_prep_slave_sg()
727 fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, in fsl_edma_prep_slave_sg()
728 dst_addr, fsl_chan->attr, soff, in fsl_edma_prep_slave_sg()
734 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); in fsl_edma_prep_slave_sg()
747 fsl_desc->iscyclic = false; in fsl_edma_prep_memcpy()
749 fsl_chan->is_sw = true; in fsl_edma_prep_memcpy()
751 fsl_chan->is_remote = true; in fsl_edma_prep_memcpy()
754 fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[0].vtcd, dma_src, dma_dst, in fsl_edma_prep_memcpy()
758 return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); in fsl_edma_prep_memcpy()
765 lockdep_assert_held(&fsl_chan->vchan.lock); in fsl_edma_xfer_desc()
767 vdesc = vchan_next_desc(&fsl_chan->vchan); in fsl_edma_xfer_desc()
770 fsl_chan->edesc = to_fsl_edma_desc(vdesc); in fsl_edma_xfer_desc()
771 fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); in fsl_edma_xfer_desc()
773 fsl_chan->status = DMA_IN_PROGRESS; in fsl_edma_xfer_desc()
774 fsl_chan->idle = false; in fsl_edma_xfer_desc()
782 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); in fsl_edma_issue_pending()
784 if (unlikely(fsl_chan->pm_state != RUNNING)) { in fsl_edma_issue_pending()
785 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); in fsl_edma_issue_pending()
790 if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc) in fsl_edma_issue_pending()
793 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); in fsl_edma_issue_pending()
801 clk_prepare_enable(fsl_chan->clk); in fsl_edma_alloc_chan_resources()
803 fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, in fsl_edma_alloc_chan_resources()
812 struct fsl_edma_engine *edma = fsl_chan->edma; in fsl_edma_free_chan_resources() local
816 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); in fsl_edma_free_chan_resources()
818 if (edma->drvdata->dmamuxs) in fsl_edma_free_chan_resources()
820 fsl_chan->edesc = NULL; in fsl_edma_free_chan_resources()
821 vchan_get_all_descriptors(&fsl_chan->vchan, &head); in fsl_edma_free_chan_resources()
823 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); in fsl_edma_free_chan_resources()
825 vchan_dma_desc_free_list(&fsl_chan->vchan, &head); in fsl_edma_free_chan_resources()
826 dma_pool_destroy(fsl_chan->tcd_pool); in fsl_edma_free_chan_resources()
827 fsl_chan->tcd_pool = NULL; in fsl_edma_free_chan_resources()
828 fsl_chan->is_sw = false; in fsl_edma_free_chan_resources()
829 fsl_chan->srcid = 0; in fsl_edma_free_chan_resources()
830 fsl_chan->is_remote = false; in fsl_edma_free_chan_resources()
832 clk_disable_unprepare(fsl_chan->clk); in fsl_edma_free_chan_resources()
840 &dmadev->channels, vchan.chan.device_node) { in fsl_edma_cleanup_vchan()
841 list_del(&chan->vchan.chan.device_node); in fsl_edma_cleanup_vchan()
842 tasklet_kill(&chan->vchan.task); in fsl_edma_cleanup_vchan()
847 * On the 32 channels Vybrid/mpc577x edma version, register offsets are
848 * different compared to ColdFire mcf5441x 64 channels edma.
852 * edma "version" and "membase" appropriately.
854 void fsl_edma_setup_regs(struct fsl_edma_engine *edma) in fsl_edma_setup_regs() argument
856 bool is64 = !!(edma->drvdata->flags & FSL_EDMA_DRV_EDMA64); in fsl_edma_setup_regs()
858 edma->regs.cr = edma->membase + EDMA_CR; in fsl_edma_setup_regs()
859 edma->regs.es = edma->membase + EDMA_ES; in fsl_edma_setup_regs()
860 edma->regs.erql = edma->membase + EDMA_ERQ; in fsl_edma_setup_regs()
861 edma->regs.eeil = edma->membase + EDMA_EEI; in fsl_edma_setup_regs()
863 edma->regs.serq = edma->membase + (is64 ? EDMA64_SERQ : EDMA_SERQ); in fsl_edma_setup_regs()
864 edma->regs.cerq = edma->membase + (is64 ? EDMA64_CERQ : EDMA_CERQ); in fsl_edma_setup_regs()
865 edma->regs.seei = edma->membase + (is64 ? EDMA64_SEEI : EDMA_SEEI); in fsl_edma_setup_regs()
866 edma->regs.ceei = edma->membase + (is64 ? EDMA64_CEEI : EDMA_CEEI); in fsl_edma_setup_regs()
867 edma->regs.cint = edma->membase + (is64 ? EDMA64_CINT : EDMA_CINT); in fsl_edma_setup_regs()
868 edma->regs.cerr = edma->membase + (is64 ? EDMA64_CERR : EDMA_CERR); in fsl_edma_setup_regs()
869 edma->regs.ssrt = edma->membase + (is64 ? EDMA64_SSRT : EDMA_SSRT); in fsl_edma_setup_regs()
870 edma->regs.cdne = edma->membase + (is64 ? EDMA64_CDNE : EDMA_CDNE); in fsl_edma_setup_regs()
871 edma->regs.intl = edma->membase + (is64 ? EDMA64_INTL : EDMA_INTR); in fsl_edma_setup_regs()
872 edma->regs.errl = edma->membase + (is64 ? EDMA64_ERRL : EDMA_ERR); in fsl_edma_setup_regs()
875 edma->regs.erqh = edma->membase + EDMA64_ERQH; in fsl_edma_setup_regs()
876 edma->regs.eeih = edma->membase + EDMA64_EEIH; in fsl_edma_setup_regs()
877 edma->regs.errh = edma->membase + EDMA64_ERRH; in fsl_edma_setup_regs()
878 edma->regs.inth = edma->membase + EDMA64_INTH; in fsl_edma_setup_regs()